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2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)最新文献

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A single-ended TG based 8T SRAM cell with increased data stability and less delay 基于单端TG的8T SRAM单元，具有更高的数据稳定性和更少的延迟
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256805
Dhananjaya Tripathy, Tarangini Manasneha, Varun Das
{"title":"A single-ended TG based 8T SRAM cell with increased data stability and less delay","authors":"Dhananjaya Tripathy, Tarangini Manasneha, Varun Das","doi":"10.1109/RTEICT.2017.8256805","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256805","url":null,"abstract":"A single-ended TG based 8-transistor (8T) static random access memory (SRAM) cell having high data stability and reduced delay is presented. The use of feedback cutting scheme reduces the read disturbance and provides better control. The employment of transmission gates (TG) as pass transistors offers less delay in comparison to the conventional CMOS logic. The results after simulation show the delay time to be 191.67 ps. The area and power consumption were found to be 36.380 μm2 and 5.105 μW respectively. The cell was implemented using Cadence UMC 180 nm technology.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121784721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and simulation of split-capacitor based three-phase four-wire shunt active power filter 分容型三相四线并联有源电力滤波器的设计与仿真
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256769
Akash V. Barva, P. Bhavsar
{"title":"Design and simulation of split-capacitor based three-phase four-wire shunt active power filter","authors":"Akash V. Barva, P. Bhavsar","doi":"10.1109/RTEICT.2017.8256769","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256769","url":null,"abstract":"This paper emphasis on design parameter and performance analysis of Split-Capacitor based Three-Phase Four-Wire Shunt Active Power Filter (3P4W2C SAPF). The 3P4W electrical distribution system have been widely used to deliver power to single-phase and/or three-phase loads. They cause harmonics, reactive power burden, unbalanced currents and excessive neutral current. This problems reduce power quality, system efficiency and increase losses in system. To overcome this issues four-wire shunt active power filter is used. In this paper 3P4W2C based on Instantaneous Reactive Power Theory (p-q Theory) and Synchronous Reference Frame Theory (SRF Theory) is simulated. All simulation done in PSIM Version 9.0 software.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115808611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PTL-and clock-pulse circuit driven novel shift register architecture ptl和时钟脉冲电路驱动的新型移位寄存器结构
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256763
Nicee Staney, S. Anand
{"title":"PTL-and clock-pulse circuit driven novel shift register architecture","authors":"Nicee Staney, S. Anand","doi":"10.1109/RTEICT.2017.8256763","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256763","url":null,"abstract":"In this paper, low power and area efficient 16-bit SISO(Serial In Serial Out) shift register is proposed. In this proposed design, the master-slave flip-flops are replaced by pulsed latches called SSASPL(Static differential Sense-Amp Shared Pulsed Latch)in order to reduce the area and power consumption. The timing issue of the pulsed latch is overcome by generating multiple non-overlap delayed short pulsed clock signals instead of using single pulsed clock signal. The shift register is divided into sub shift registers to reduce the number of clock buffers. Two circuits of256-bitand a 16-bitshift register(driven by CMOS-AND based clock pulse generator) are also implemented for study and comparison with proposed design. The proposed 16-bit shift register is driven by PTL-AND based clock pulse generator and is implemented using CMOS 0.18μm technology in Cadence Virtuoso. The proposed 16-bit shift register using PTL-AND clock pulse circuit consumes 14% less power and 4% less area compared to CMOS-AND pulse generation circuit.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132027134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
To provide an easy and fast means of identification of blood group using IR sensors 利用红外传感器提供一种简单快速的血型识别方法
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256666
Sandip D. Sahane, U. Chaskar
{"title":"To provide an easy and fast means of identification of blood group using IR sensors","authors":"Sandip D. Sahane, U. Chaskar","doi":"10.1109/RTEICT.2017.8256666","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256666","url":null,"abstract":"Identification of blood group plays a vital role in the medical field for any treatment. Miss-transfusion of blood will lead to many complications. This method provides an easy and fast means of identification of blood groups. The difference in the amount absorption by each blood group is exploited so as to categorize the blood groups. The light from the pulsating IR LED is passed through the blood sample and the transmitted light is then detected, conditioned and is converted into voltage signal. The variations in the intensity of the received signal due to the absorption of blood for different blood groups are translated into corresponding voltage changes, to classify the blood groups.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132518341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of CELP encoder using Vivado HLS 使用Vivado HLS实现CELP编码器
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256836
Prakash C S Abhijna, N. Sangeetha, J. R. Sagar, R. Rahul, Gaurav Gupta
{"title":"Implementation of CELP encoder using Vivado HLS","authors":"Prakash C S Abhijna, N. Sangeetha, J. R. Sagar, R. Rahul, Gaurav Gupta","doi":"10.1109/RTEICT.2017.8256836","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256836","url":null,"abstract":"Eminent research scholars have confirmed the feasibility of CELP principle and its implementation which overcomes the hurdles of primitive algorithms like RELP, where in the residual signal information can't be reconstructed further, but which is possible in CELP implemented technique which produces good quality speech at low bit rates. This paper's central idea is the design and implementation of CELP encoder. This LPC technique achieves LP analysis of speech by extracting the LP parameters and coefficients and utilizes a scheme to search a codebook and compute the excitation signal. With the help of Vivado HLS we have implemented synthesizable set of codes and shown the report including timing, latency and hardware utilization.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130221521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design and implementation of low power mitchell algorithm based logarithmic multiplier 基于低功耗mitchell算法的对数乘法器的设计与实现
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256828
H. Ranjitha, K. Pooja, RAVISH ARADHYA H V
{"title":"Design and implementation of low power mitchell algorithm based logarithmic multiplier","authors":"H. Ranjitha, K. Pooja, RAVISH ARADHYA H V","doi":"10.1109/RTEICT.2017.8256828","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256828","url":null,"abstract":"Multiplication is a significant operation in signal processing but slow and complex leading to high power consumption and area. Digital Signal Processing repetitively uses multiplication to carry out computations. One feasible solution to simplify multiplication is to use Logarithmic Number System (LNS) instead on Binary. LNS method greatly reduces the computation time but with a trade-off in accuracy. However, we can use this approach in DSP in which speedy computation is of greater concern than accuracy. This paper presents a low power logarithmic multiplication approach aimed to achieve faster computation. The hardware implementation involves very primitive components like adder, shifter and counter which consume less power. Further, adiabatic logic is used at circuit level to reduce power consumption. Power analysis is carried out for traditional CMOS logic and Adiabatic logic using Cadence Virtuoso. The proposed fully adiabatic Switch Rail Charge Recovery Logic (SCRL) and quasi adiabatic Efficient Charge Recovery Logic (ECRL) based logarithmic multiplier is proved to reduce power dissipation by a factor of 81.36 % and 33.4 % respectively than CMOS implementation.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131802830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Protecting data from masquerades using control flows 使用控制流保护数据免受伪装
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256608
Pranayanath Reddy Anantula, G. Someswar
{"title":"Protecting data from masquerades using control flows","authors":"Pranayanath Reddy Anantula, G. Someswar","doi":"10.1109/RTEICT.2017.8256608","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256608","url":null,"abstract":"Protecting data from intruders and hackers in cloud computing environment has become imperative. There are standard security techniques that take care of identifying the valid user. Even though there are in place strong cryptographic techniques, hackers may trespass and enter the system using some user credentials. Hacker can then have access to the system and the data present in it. The challenge we face in this situation is, even if hacker get access to the system he/she must be limited to access the data. This can be done by streamlining the pattern or behavior of the users and protecting critical data from being accessed by hackers and intruders. Cloud service providers can provide high level of security at authentication level, not at authorization level. Organizations need to add additional mechanism to ensure strong authentication and authorization process from their end. In this paper we have proposed framework to deal with privacy in cloud applications, by using customized control flows to ensuring strong authentication and authorization process.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130697418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and design of compact digital phase shifter using substrate integrated waveguide 基于基板集成波导的紧凑型数字移相器的分析与设计
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256901
Shweta Koulagi, M. Sujatha
{"title":"Analysis and design of compact digital phase shifter using substrate integrated waveguide","authors":"Shweta Koulagi, M. Sujatha","doi":"10.1109/RTEICT.2017.8256901","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256901","url":null,"abstract":"Most of the researches are attracted by Substrate Integrated Waveguide (SIW) based devices due to small size, less cost, less weight, and low loss. The technology of Substrate Integrated Waveguide takes the advantages of both waveguides and planar transmission lines. The Substrate Integrated Waveguides fabrication in planar form is done using standard PCB. This paper includes analysis of SIWs using commercially available low cost FR4 material with thickness h=0.8mm. They were designed to operate at different cut off frequencies (8GHz, 16GHz, and 32GHz). The simulation results show that there is a good agreement between the response of SIW and conventional metallic waveguides. This paper also gives the analysis of phase shifter using SIW to operate at 10GHz. It is demonstrated that phase of the signal can be varied by inserting post inside the SIW and parametric studies proves that phase can be changed over a larger range by varying positions of the post.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131220652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Subthreshold adiabatic logic (SAL) based building blocks for combinational system design 基于阈下绝热逻辑(SAL)的组合系统设计构件
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256565
K. Ranjith, A. Chavan, RAVISH ARADHYA H V
{"title":"Subthreshold adiabatic logic (SAL) based building blocks for combinational system design","authors":"K. Ranjith, A. Chavan, RAVISH ARADHYA H V","doi":"10.1109/RTEICT.2017.8256565","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256565","url":null,"abstract":"Sub-threshold Adiabatic Logic (SAL), is a power saving technique that could be used for applications which demands very low power consumption and are not performance intensive. In this paper SAL is studied and the basic building blocks for combinational systems are implemented and simulated using Cadence in 45nm technology node. Results are compared with corresponding CMOS implementations considering power delivered from source, delay in signal propagation and computed Power Delay Product (PDP). It is observed that relative power delivered from the source is reduced by almost 50dB in case of SAL compared with respective CMOS implementation.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131227041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Pedometric CAPTCHA for mobile Internet users 移动互联网用户步数验证码
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-01 DOI: 10.1109/RTEICT.2017.8256667
S. Kulkarni, H. Fadewar
{"title":"Pedometric CAPTCHA for mobile Internet users","authors":"S. Kulkarni, H. Fadewar","doi":"10.1109/RTEICT.2017.8256667","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256667","url":null,"abstract":"CAPTCHA requires proof of humanness, thus every CAPTCHA design strives to trace human skills in its user. Many human skills have been explored for designing robust CAPTCHA. In this paper we propose a novel CAPTCHA design for mobile devices. Proposed Pedometric CAPTCHA uses human capability of walking. This paper aims to provide algorithm for implementing Pedometric CAPTCHA, analyze its' usability for persons with various disabilities, perform security analysis and study of user experience. As attacks on CAPTCHA are performed by software bots, human capability of walking or creating acceleration in a mobile device can be effectively used to thwart bots. Usability analysis shows that Pedometric CAPTCHA is accessible for almost all types of disabilities except for the complete motor disability. Study of user experience depicts that 92.2% of the 64 volunteers found the Pedometric CAPTCHA interface to be easy to navigate.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133544681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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