A single-ended TG based 8T SRAM cell with increased data stability and less delay

Abstract

A single-ended TG based 8-transistor (8T) static random access memory (SRAM) cell having high data stability and reduced delay is presented. The use of feedback cutting scheme reduces the read disturbance and provides better control. The employment of transmission gates (TG) as pass transistors offers less delay in comparison to the conventional CMOS logic. The results after simulation show the delay time to be 191.67 ps. The area and power consumption were found to be 36.380 μm2 and 5.105 μW respectively. The cell was implemented using Cadence UMC 180 nm technology.