基于低功耗mitchell算法的对数乘法器的设计与实现

H. Ranjitha, K. Pooja, RAVISH ARADHYA H V
{"title":"基于低功耗mitchell算法的对数乘法器的设计与实现","authors":"H. Ranjitha, K. Pooja, RAVISH ARADHYA H V","doi":"10.1109/RTEICT.2017.8256828","DOIUrl":null,"url":null,"abstract":"Multiplication is a significant operation in signal processing but slow and complex leading to high power consumption and area. Digital Signal Processing repetitively uses multiplication to carry out computations. One feasible solution to simplify multiplication is to use Logarithmic Number System (LNS) instead on Binary. LNS method greatly reduces the computation time but with a trade-off in accuracy. However, we can use this approach in DSP in which speedy computation is of greater concern than accuracy. This paper presents a low power logarithmic multiplication approach aimed to achieve faster computation. The hardware implementation involves very primitive components like adder, shifter and counter which consume less power. Further, adiabatic logic is used at circuit level to reduce power consumption. Power analysis is carried out for traditional CMOS logic and Adiabatic logic using Cadence Virtuoso. The proposed fully adiabatic Switch Rail Charge Recovery Logic (SCRL) and quasi adiabatic Efficient Charge Recovery Logic (ECRL) based logarithmic multiplier is proved to reduce power dissipation by a factor of 81.36 % and 33.4 % respectively than CMOS implementation.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design and implementation of low power mitchell algorithm based logarithmic multiplier\",\"authors\":\"H. Ranjitha, K. Pooja, RAVISH ARADHYA H V\",\"doi\":\"10.1109/RTEICT.2017.8256828\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multiplication is a significant operation in signal processing but slow and complex leading to high power consumption and area. Digital Signal Processing repetitively uses multiplication to carry out computations. One feasible solution to simplify multiplication is to use Logarithmic Number System (LNS) instead on Binary. LNS method greatly reduces the computation time but with a trade-off in accuracy. However, we can use this approach in DSP in which speedy computation is of greater concern than accuracy. This paper presents a low power logarithmic multiplication approach aimed to achieve faster computation. The hardware implementation involves very primitive components like adder, shifter and counter which consume less power. Further, adiabatic logic is used at circuit level to reduce power consumption. Power analysis is carried out for traditional CMOS logic and Adiabatic logic using Cadence Virtuoso. The proposed fully adiabatic Switch Rail Charge Recovery Logic (SCRL) and quasi adiabatic Efficient Charge Recovery Logic (ECRL) based logarithmic multiplier is proved to reduce power dissipation by a factor of 81.36 % and 33.4 % respectively than CMOS implementation.\",\"PeriodicalId\":342831,\"journal\":{\"name\":\"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RTEICT.2017.8256828\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTEICT.2017.8256828","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

乘法运算是信号处理中的重要运算,但速度慢且复杂,导致功耗和面积大。数字信号处理重复使用乘法来进行计算。简化乘法的一个可行的解决方案是在二进制上使用对数数系统(LNS)。LNS方法大大减少了计算时间,但牺牲了精度。然而,我们可以在DSP中使用这种方法,其中计算速度比精度更重要。本文提出了一种低功耗的对数乘法方法,旨在实现更快的计算速度。硬件实现包括非常原始的组件,如加法器、移位器和计数器,它们消耗较少的功率。此外,在电路级使用绝热逻辑以降低功耗。利用Cadence Virtuoso对传统CMOS逻辑和绝热逻辑进行功耗分析。实验证明,基于全绝热开关轨电荷恢复逻辑(SCRL)和准绝热高效电荷恢复逻辑(ECRL)的对数乘法器的功耗比CMOS器件分别降低81.36%和33.4%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and implementation of low power mitchell algorithm based logarithmic multiplier
Multiplication is a significant operation in signal processing but slow and complex leading to high power consumption and area. Digital Signal Processing repetitively uses multiplication to carry out computations. One feasible solution to simplify multiplication is to use Logarithmic Number System (LNS) instead on Binary. LNS method greatly reduces the computation time but with a trade-off in accuracy. However, we can use this approach in DSP in which speedy computation is of greater concern than accuracy. This paper presents a low power logarithmic multiplication approach aimed to achieve faster computation. The hardware implementation involves very primitive components like adder, shifter and counter which consume less power. Further, adiabatic logic is used at circuit level to reduce power consumption. Power analysis is carried out for traditional CMOS logic and Adiabatic logic using Cadence Virtuoso. The proposed fully adiabatic Switch Rail Charge Recovery Logic (SCRL) and quasi adiabatic Efficient Charge Recovery Logic (ECRL) based logarithmic multiplier is proved to reduce power dissipation by a factor of 81.36 % and 33.4 % respectively than CMOS implementation.
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