{"title":"Subthreshold adiabatic logic (SAL) based building blocks for combinational system design","authors":"K. Ranjith, A. Chavan, RAVISH ARADHYA H V","doi":"10.1109/RTEICT.2017.8256565","DOIUrl":null,"url":null,"abstract":"Sub-threshold Adiabatic Logic (SAL), is a power saving technique that could be used for applications which demands very low power consumption and are not performance intensive. In this paper SAL is studied and the basic building blocks for combinational systems are implemented and simulated using Cadence in 45nm technology node. Results are compared with corresponding CMOS implementations considering power delivered from source, delay in signal propagation and computed Power Delay Product (PDP). It is observed that relative power delivered from the source is reduced by almost 50dB in case of SAL compared with respective CMOS implementation.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTEICT.2017.8256565","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Sub-threshold Adiabatic Logic (SAL), is a power saving technique that could be used for applications which demands very low power consumption and are not performance intensive. In this paper SAL is studied and the basic building blocks for combinational systems are implemented and simulated using Cadence in 45nm technology node. Results are compared with corresponding CMOS implementations considering power delivered from source, delay in signal propagation and computed Power Delay Product (PDP). It is observed that relative power delivered from the source is reduced by almost 50dB in case of SAL compared with respective CMOS implementation.