PTL-and clock-pulse circuit driven novel shift register architecture

In this paper, low power and area efficient 16-bit SISO(Serial In Serial Out) shift register is proposed. In this proposed design, the master-slave flip-flops are replaced by pulsed latches called SSASPL(Static differential Sense-Amp Shared Pulsed Latch)in order to reduce the area and power consumption. The timing issue of the pulsed latch is overcome by generating multiple non-overlap delayed short pulsed clock signals instead of using single pulsed clock signal. The shift register is divided into sub shift registers to reduce the number of clock buffers. Two circuits of256-bitand a 16-bitshift register(driven by CMOS-AND based clock pulse generator) are also implemented for study and comparison with proposed design. The proposed 16-bit shift register is driven by PTL-AND based clock pulse generator and is implemented using CMOS 0.18μm technology in Cadence Virtuoso. The proposed 16-bit shift register using PTL-AND clock pulse circuit consumes 14% less power and 4% less area compared to CMOS-AND pulse generation circuit.