2013 European Conference on Circuit Theory and Design (ECCTD)最新文献_第9页

A study of RF oscillator reliability in nanoscale CMOS 纳米级CMOS射频振荡器可靠性研究

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662205

M. Babaie, R. Staszewski

引用次数: 22

Critical role of initial condition in the dynamics of memristive systems: Orbital narrowing revisited 初始条件在记忆系统动力学中的关键作用:眼眶变窄

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662209

Weiran Cai, R. Tetzlaff, F. Ellinger

{"title":"Critical role of initial condition in the dynamics of memristive systems: Orbital narrowing revisited","authors":"Weiran Cai, R. Tetzlaff, F. Ellinger","doi":"10.1109/ECCTD.2013.6662209","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662209","url":null,"abstract":"This paper explores the characterization of memristive systems utilizing the characteristive curve of state and analyze the special role of initial condition in such history-dependent systems. The specifically studied system focuses on the titanium dioxide memristor based on the nonlinear ionic drift model of Joglekar. We derive first the characteristic curve of state (CCOS) as the analytical solution of the model to any integer index in the Gaussian hypergeometric form, based on which a characterization approach is then developed. The approach simply converts the complicated history-dependent dynamics into a mapping on the state-flux phase plane, expressing the initial condition as a pure translation along the flux axis, which is analogous to the characterization method for transistors. With this geometric view, we observe that the initial condition operates as an operation point for a memristive system and can effectively influence the orbital shape: the same input signal can produce two distinct orbital shapes when the initial conditions differ. From another point, there ought to be two factors giving rise to the orbital narrowing phenomenon: the frequency and the initial condition. It is pointed out that this is purely caused by the nonlinearity in the model.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131854532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Complex dynamics in neuromorphic memristor circuits 神经形态记忆电阻电路中的复杂动力学

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662221

F. Corinto, M. Gilli, A. Ascoli, R. Tetzlaff

引用次数: 5

The spatial Cauchy problem for a dissipative infinite quantum waveguide supporting a single propagating mode 支持单一传播模式的耗散无限量子波导的空间柯西问题

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662282

P. Civalleri, M. Gilli, M. Bonnin

引用次数: 0

Reliable and efficient phase noise simulation of mixed-mode integer-N Phase-Locked Loops 可靠高效的混合模式整数n锁相环相位噪声仿真

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662284

Matteo Biggio, F. Bizzarri, A. Brambilla, G. Carlini, M. Storace

引用次数: 10

CMOS photodiode model and HDL implementation CMOS光电二极管模型及HDL实现

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662192

B. Blanco-Filgueira, P. López, Manuel Suárez-Cambre, J. Roldán

引用次数: 1

Study of peak and backoff efficiency of different power amplifier classes in outphasing systems 同相系统中不同功率放大器的峰值效率和后退效率研究

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662245

K. Aggour, R. Negra

引用次数: 1

Strategies for finding a bandwidth-optimal topology for impedance matching 为阻抗匹配寻找带宽最优拓扑的策略

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662333

A. Lehtovuori, R. Valkonen

引用次数: 7

An adaptive approach to on-chip CMOS ramp generation for high resolution single-slope ADCs 用于高分辨率单斜率adc的片上CMOS斜坡生成的自适应方法

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662334

Samuel Sordo Ibáñez, B. Piñero-García, S. Espejo-Meana, A. Ragel-Morales, J. Caceres, M. Munoz-Diaz, L. Carranza-González, A. Arias-Drake, J. M. Mora-Gutierrez, M. A. Lagos-Florido

{"title":"An adaptive approach to on-chip CMOS ramp generation for high resolution single-slope ADCs","authors":"Samuel Sordo Ibáñez, B. Piñero-García, S. Espejo-Meana, A. Ragel-Morales, J. Caceres, M. Munoz-Diaz, L. Carranza-González, A. Arias-Drake, J. M. Mora-Gutierrez, M. A. Lagos-Florido","doi":"10.1109/ECCTD.2013.6662334","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662334","url":null,"abstract":"Many image sensors employ column-parallel ADCs in their readout structures. Single-slope ADCs are ideally suited for these multi-channel applications due to their simplicity, low power and small overall area. The ramp generator, shared by all the converters in the readout architecture, is a key element that has a direct effect in the transfer characteristic of single-slope ADCs. Because a digital counter is inherently present in this conversion scheme, one common practice is to use a digital-to-analog converter driven by the counter to generate the ramp. Given the direct relationship between the DAC and the ADC transfer characteristics, one of the main issues is to ensure a sufficient linearity of the DAC, with special emphasis on its monotonicity. Very often, in particular when medium to high resolutions are aimed, this requires calibration of the DAC, which must be repeated every once in a while to account for temperature, process, power supply, and aging variations. This paper presents an inherently monotonic ramp generator with high levels of linearity and stability against any expected source of variations, combined with a very efficient realization and an inherent automatic adaptability to different resolutions. The ramp generator has been designed using radiation hardening by design (RHBD) techniques, allowing its use in space applications.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123711790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A low noise single-ended to differential linear charge sampling SC-VGA for second harmonic cardiac ultrasound imaging 用于二次谐波心脏超声成像的低噪声单端差分线性电荷采样SC-VGA

2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662288

P. Wang, T. Ytterdal, T. Halvorsrod

{"title":"A low noise single-ended to differential linear charge sampling SC-VGA for second harmonic cardiac ultrasound imaging","authors":"P. Wang, T. Ytterdal, T. Halvorsrod","doi":"10.1109/ECCTD.2013.6662288","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662288","url":null,"abstract":"A low noise single-ended to differential linear switched capacitor variable gain amplifier (SC-VGA) is designed in a 0.18μm CMOS technology for 4MHz center frequency (fs) 26-MHz ultrasound imaging. To fit the higher source impedance from gradually scaled piezo-electric transducers (PZT) in ultrasound imaging systems, a charge sampling amplifier with a fixed integration time as the first stage exhibits the lower noise, and higher sensitivity compared to the conventional voltage sampling amplifiers. The second voltage sampling stage converts the single-ended input to differential outputs with an exponential gain control which exploits an 8b binary capacitor (CAP) array, and the gain varies dB-in-linear from -14dB to 14dB. To reduce the capacitance spread for a binary-weighted 8b CAP array, the array is segmented between the upper 4b and lower 4b by a divider capacitor. Simulation results show the analog part of proposed amplifier consumes 1.25mA at 1.8V, has HD2 -62dB, HD3 -79dB at 150mV output Vpp, and the input referred noise (IRN) is 6.56pA/√Hz at 4MHz and 25.3nArms at a sampling frequency (fs) of 30MHz. The layout size is 310μm×370μm.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"20 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121001469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3