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2013 European Conference on Circuit Theory and Design (ECCTD)最新文献

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Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs 用于高速adc的新型动态锁存比较器的设计与分析
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662236
Yan-Chao Huang, H. Schleifer, D. Killat
{"title":"Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs","authors":"Yan-Chao Huang, H. Schleifer, D. Killat","doi":"10.1109/ECCTD.2013.6662236","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662236","url":null,"abstract":"A novel dynamic latched comparator with reduced kickback noise for high-speed ADCs is presented. Dynamic latched comparators suffer from kickback noise. Especially the common-mode kickback noise becomes even more critical in applications with asymmetric input. By using common source input transistors and a decoupling mechanism the novel dynamic latched comparator produces much lower common-mode kickback noise, while the differential kickback noise is also significantly reduced. The simulated results show that the proposed comparator not only produces less than one third of the common-mode kickback noise of other typical dynamic latched comparators, but also settles faster.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122911271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Behavioral model of a continuous current integrator with time discrete feedback and sampling 具有时间离散反馈和采样的连续电流积分器的行为模型
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662252
J. Gorner, Johannes Uhlig, Stefan Hänzsche, R. Schüffny
{"title":"Behavioral model of a continuous current integrator with time discrete feedback and sampling","authors":"J. Gorner, Johannes Uhlig, Stefan Hänzsche, R. Schüffny","doi":"10.1109/ECCTD.2013.6662252","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662252","url":null,"abstract":"This paper proposes an analytical model for current integrator with a continuous current input signal, a continuous voltage output signal, with time discrete feedback and sampling. Such an integrator is suited as first integrator within a delta sigma (ΔΣ) modulator performing analog to digital conversion of a current input signal. Capacitive or current feedback can be used for keeping the integrator within the range of operation. The model considers slew-rate and bandwidth limited settling, parasitic capacitances, and non-linear effects. Simulink is used to explore the circuit design space for the first integrator of a 4th order hybrid incremental (I-ΔΣ) modulator.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124824849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL 相位预测全数字锁相环数时转换器增益估计
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662211
J. Zhuang, R. Staszewski
{"title":"Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL","authors":"J. Zhuang, R. Staszewski","doi":"10.1109/ECCTD.2013.6662211","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662211","url":null,"abstract":"We propose a gain estimation technique of a digital-to-time converter (DTC) and a time-to-digital converter (TDC) intended for an all-digital phase-locked loop (ADPLL) that is based on a recently introduced phase-prediction (PP) technique. Such a PP-ADPLL reduces the timing range and thus complexity of the fractional part of the phase detection mechanism. The conventional TDC gain estimation methods based on measuring the DCO clock period are not feasible for PP-ADPLLs due to the TDC timing range being much smaller than one DCO clock period. The proposed gain estimation method can run concurrently with the normal ADPLL phase locking process and its feasibility is confirmed through behavioral simulations. Although the estimation method is specifically proposed for the PP-ADPLL, its operating principle can also be applied to conventional ADPLL architectures that require an accurate TDC gain estimation.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128909043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Experimental validation of DAC with nested bus-splitting EFM4 DDSM 基于嵌套总线分割EFM4 DDSM的DAC实验验证
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662198
Hongjia Mo, Michael Peter Kennedy, Vincent O’Brien, Brendan Mullane
{"title":"Experimental validation of DAC with nested bus-splitting EFM4 DDSM","authors":"Hongjia Mo, Michael Peter Kennedy, Vincent O’Brien, Brendan Mullane","doi":"10.1109/ECCTD.2013.6662198","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662198","url":null,"abstract":"This paper presents measured results for a fourth order nested bus-splitting Error Feedback Modulator (EFM4) with dynamic element matching and a four-bit DAC. The nested bus-splitting EFM4 can run approximately 38% faster than a conventional EFM4 on a Xilinx Virtex 5, with negligible degradation in spectral performance.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124528268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Stabilizing control based on Stability Transformation Method for switching power converter 基于稳定变换法的开关电源变换器稳定控制
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662337
Nguyen Thi My Hanh, T. Tsubone
{"title":"Stabilizing control based on Stability Transformation Method for switching power converter","authors":"Nguyen Thi My Hanh, T. Tsubone","doi":"10.1109/ECCTD.2013.6662337","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662337","url":null,"abstract":"A dynamic controller based on Stability Transformation Method (STM) has been used to stabilize unknown unstable periodic orbits (UPOs) in dynamical systems. The advantage of the control method is that it can stabilize the UPOs without information of location about the target orbit. In this study, we introduce a novel control method based on STM to stabilize UPOs in DC-DC switching power converter. The idea of the proposed method is to apply temporal perturbations to switching time, where the perturbation can be calculated exactly by using a dynamic controller based on STM. Therefore, our control method can stabilize unknown UPOs. The effectiveness of proposed method is verified by theoretical analysis and circuit simulator.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120882543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multiple metastable rotating waves and long transients in cooperative CNN rings 协同CNN环中的多亚稳旋转波和长瞬态
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662265
M. D. Marco, M. Forti, B. Garay, M. Koller, L. Pancioni
{"title":"Multiple metastable rotating waves and long transients in cooperative CNN rings","authors":"M. D. Marco, M. Forti, B. Garay, M. Koller, L. Pancioni","doi":"10.1109/ECCTD.2013.6662265","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662265","url":null,"abstract":"This paper further investigates on the phenomena leading to the existence of long transient oscillations in a class of cooperative cellular neural network (CNN) rings. It is shown, by analytic arguments, numerical simulations, and laboratory experiments, that the transients are due to the existence of several symmetric and nonsymmetric metastable rotating waves in the CNN ring which are strongly attracting along the stable manifold and weakly repelling along the unstable manifold.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121052063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An LC CMOS injection-locked frequency divider for divide-by-two and divide-by-three operation 一种LC CMOS注入锁定分频器，用于除二和除三操作
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662295
Malik Summair Asghar, M. A. Awan, Z. Huang, Wenyuan Li, Michael Peter Kennedy, A. Buonomo, A. L. Schiavo
{"title":"An LC CMOS injection-locked frequency divider for divide-by-two and divide-by-three operation","authors":"Malik Summair Asghar, M. A. Awan, Z. Huang, Wenyuan Li, Michael Peter Kennedy, A. Buonomo, A. L. Schiavo","doi":"10.1109/ECCTD.2013.6662295","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662295","url":null,"abstract":"Numerous circuit topologies have been proposed for divide-by-m injection-locked frequency dividers (ILFDs), most of which have been optimized for division by even numbers, especially divide-by-2. It has been more difficult to realize division by odd numbers, such as divide-by-3. This paper describes a CMOS injection locked frequency divider (ILFD) that can operate equally well in both divide-by-two and divide-by-three modes. The ILFD is based on a cross-coupled CMOS LC-tank oscillator having capacitive and direct injection via both NMOS and PMOS transistors connected across the LC tank. The circuit is similar to a conventional CMOS ILFD for divide-by-two operation with direct injection, but it combines the effects of two independent injection techniques to maximize the width of its divide-by-three locking range. The paper presents the circuit architecture, SPICE simulations, and experimental measurements.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121769485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Syntheses of a PSPICE model of a titanium-dioxide memristor and Wien memristor generator 二氧化钛忆阻器PSPICE模型及Wien忆阻器发生器的合成
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662302
V. Mladenov, S. Kirilov
{"title":"Syntheses of a PSPICE model of a titanium-dioxide memristor and Wien memristor generator","authors":"V. Mladenov, S. Kirilov","doi":"10.1109/ECCTD.2013.6662302","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662302","url":null,"abstract":"In this paper a PSPICE model of the equivalent circuit of the titanium-dioxide memristor is created based on its current-voltage relationship and using linear ionic drift model. By use of this computer model a Wien memristor generator is created. The oscillator circuit is analyzed and the basic relationships and time diagrams are given. The phase portrait of the system is also presented. The regulation of the output voltage magnitude and of the frequency is realized by changing the memristor's states using external pulse voltage sources. In the end, some concluding remarks about the memristor Wien generator investigated are given.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122906901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A chaos based integrated jitter booster circuit for true random number generators 一种基于混沌的真随机数发生器集成抖动增强电路
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662257
I. Çiçek, Günhan Dündar
{"title":"A chaos based integrated jitter booster circuit for true random number generators","authors":"I. Çiçek, Günhan Dündar","doi":"10.1109/ECCTD.2013.6662257","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662257","url":null,"abstract":"In this work, we present a chaos based integrated jitter booster circuit for use in multiple oscillator sampling true random number generator architecture. Multiple ring oscillator based true random number generators need significant number of rings for accumulating the intrinsic jitter of inverters to a useful level. Thus, they occupy large silicon area and consume considerable amount of power. The proposed circuit offers an alternative approach for boosting jitter using the chaotic dynamics generated by non-linear coupling of two ring oscillators that require fewer number of components. The simplicity of the proposed circuit offers high integration potential with inherent low area and power consumption advantages. Chaotic dynamics of the circuit was studied using both numerical and circuit simulations. Measurement results of the test chip implemented at 250nm CMOS technology node confirmed chaotic behavior and jitter boosting capability. To the very best of our knowledge this is the first integrated circuit implementation of a chaotic circuit based on digital gates.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126612443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A high-speed QR decomposition processor for carrier-aggregated LTE-A downlink systems 一种用于载波聚合LTE-A下行系统的高速QR分解处理器
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662237
Rakesh Gangarajaiah, Liang Liu, M. Stala, P. Nilsson, O. Edfors
{"title":"A high-speed QR decomposition processor for carrier-aggregated LTE-A downlink systems","authors":"Rakesh Gangarajaiah, Liang Liu, M. Stala, P. Nilsson, O. Edfors","doi":"10.1109/ECCTD.2013.6662237","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662237","url":null,"abstract":"This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4×4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65nm CMOS technology, the processor occupies a core area of 0.77mm2 and produces 72MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 127 mW.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125783903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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