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2017 International Conference on Circuits, System and Simulation (ICCSS)最新文献

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A high-performance branch predictor design considering memory capacity limitations 考虑内存容量限制的高性能分支预测器设计
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023180
Ha Kyoum Kim, Hanjo Kim, C. M. Eun, Hyun Hak Cho, O. H. Jeong
{"title":"A high-performance branch predictor design considering memory capacity limitations","authors":"Ha Kyoum Kim, Hanjo Kim, C. M. Eun, Hyun Hak Cho, O. H. Jeong","doi":"10.1109/CIRSYSSIM.2017.8023180","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023180","url":null,"abstract":"Pipeline flush due to the flow change of instruction can be a huge degradation factor in modern processors since the branch instructions consist of more than 20 % of all instructions when running a program. However, with a characteristic called branch locality, the result of branch execution is predictable. By utilizing branch locality, there have been a lot of researches to improve the prediction rate of branch predictor however, most of these did not consider the memory capacity so that they cannot be implemented to the embedded systems. Therefore, we propose a new scheme with high prediction rate while maintaining low memory consumption. The new scheme uses an XOR gate to diversify the Pattern History Table (PHT) index. However, the last 6 bits of the index are replaced with PC addresses to enhance the distinction ability of branch instruction addresses. The simulation was executed using SimpleScalar 3.0 simulator, and benchmarks from SPEC CPU2000. Based on the simulation result, this new structure achieved higher prediction rate while maintaining the low memory consumption. Consequently, the new scheme is the most appropriate branch predictor among comparison group presented in this paper.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116919455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A scheme of synchronization calibration between high-speed acquisition boards 一种高速采集板间同步标定方案
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-01 DOI: 10.1109/CIRSYSSIM.2017.8023182
Longhui Wang, Guoman Liu, Qian Liu
{"title":"A scheme of synchronization calibration between high-speed acquisition boards","authors":"Longhui Wang, Guoman Liu, Qian Liu","doi":"10.1109/CIRSYSSIM.2017.8023182","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023182","url":null,"abstract":"In high-speed acquisition system, timing sequence of sampling gate signal and SYNC reset signal may affect synchronization between high-speed acquisition boards (called board synchronization). The problem of board synchronization can be solved by delaying these two signals. In order to ensure board synchronization, a scheme was proposed to estimate reasons for abnormal synchronization according to the difference between boards and calibrated delay parameters of sampling gate signal and SYNC reset signal. When the difference between boards was m sampling points (m is sampling frequency dividing ratio), the abnormal synchronization was caused by sampling gate signal. When the difference between boards was 1 sampling point, the abnormal synchronization was caused by SYNC reset signal. It was effective to adjust the delay parameter of sampling gate signal and the delay parameter of SYNC reset signal to ensure board synchronization. Through test, board synchronization deviation was not more than 20ps. This scheme does not need ergodic calibration of all delay parameters, largely increases efficiency.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114474569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Based on improved subset sampling algorithm for SEU physical simulation 基于改进子集采样算法的单单元物理仿真
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-01 DOI: 10.1109/CIRSYSSIM.2017.8023192
Zhu Ming, Kang He, Zhu Hengjing, Yu Qingkui, Sun Yi, Tang Min
{"title":"Based on improved subset sampling algorithm for SEU physical simulation","authors":"Zhu Ming, Kang He, Zhu Hengjing, Yu Qingkui, Sun Yi, Tang Min","doi":"10.1109/CIRSYSSIM.2017.8023192","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023192","url":null,"abstract":"This paper proposes an improved subset sampling algorithm based on machine learning. The physical simulation is executed on SEU cross section of SRAM, which can effectively simulate the real physical process in the single particle effect and reduce the simulation time. The simulation results are good agreement with the experimental results. The proposed method is validly verified.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121263300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Controller and observer design for anti-angiogenic tumor treatment 抗血管生成肿瘤治疗的控制器和观测器设计
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-01 DOI: 10.1109/CIRSYSSIM.2017.8023181
C. Tunceroglu, U. Hasirci
{"title":"Controller and observer design for anti-angiogenic tumor treatment","authors":"C. Tunceroglu, U. Hasirci","doi":"10.1109/CIRSYSSIM.2017.8023181","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023181","url":null,"abstract":"This paper concerns design and numerical simulation for anti-angiogenic tumor treatment for the tumors cause women breast cancer. The paper first provides an exact model knowledge controller to drive tumor volume to a desired trajectory, and then explains the design of an observer for the carrying capacity of the vascular network. Lyapunov-like arguments are used to prove the stability of the system. Numerical simulation results are also presented to show the feasibility of the proposed controller and observer.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115661798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 28mW 320MHz 3rd-order continuous-time time-interleaved delta-sigma modulator with 10MHz bandwidth and 12 bits of resolution 28mW 320MHz三阶连续时间时间交错δ - σ调制器，带宽10MHz，分辨率12位
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-01 DOI: 10.1109/CIRSYSSIM.2017.8023207
J. Talebzadeh, I. Kale
{"title":"A 28mW 320MHz 3rd-order continuous-time time-interleaved delta-sigma modulator with 10MHz bandwidth and 12 bits of resolution","authors":"J. Talebzadeh, I. Kale","doi":"10.1109/CIRSYSSIM.2017.8023207","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023207","url":null,"abstract":"This paper presents a 3rd-order two-path Continuous-Time Time-Interleaved (CTTI) delta-sigma modulator which is implemented in standard 90nm CMOS technology. The architecture uses a novel method to solve the delayless feedback path issue arising from the sharing of integrators between paths. The clock frequency of the modulator is 320MHz but integrators, quantizers and DACs operate at 160MHz. The modulator achieves a dynamic range of 12 bits over a bandwidth of 10MHz and dissipates only 28mW of power from a 1.8-V supply.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127408376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Redundant logic insertion and fault tolerance improvement in combinational circuits 组合电路中冗余逻辑插入与容错改进
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-01 DOI: 10.1109/CIRSYSSIM.2017.8023171
Padmanabhan Balasubramanian, R. T. Naayagi
{"title":"Redundant logic insertion and fault tolerance improvement in combinational circuits","authors":"Padmanabhan Balasubramanian, R. T. Naayagi","doi":"10.1109/CIRSYSSIM.2017.8023171","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023171","url":null,"abstract":"This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125555676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Intelligent management and control of received wireless power 对接收的无线电源进行智能管理和控制
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-01 DOI: 10.1109/CIRSYSSIM.2017.8023186
Thabat Thabet, J. Woods
{"title":"Intelligent management and control of received wireless power","authors":"Thabat Thabet, J. Woods","doi":"10.1109/CIRSYSSIM.2017.8023186","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023186","url":null,"abstract":"The concept of powering a remote device without wires is known as a wireless power transfer system. Some applications employ batteries while others use storage capacitors instead. In either case, it is necessary to transfer enough power to enable the receiver to do the required work. This paper presents an intelligent algorithm to manage received wireless power to do useful work even though there is insufficient power to do the work directly. The example ultra-low power microcontroller discussed here is the ATTiny85 although the approach is applicable to a whole family of similar micros. The algorithm used makes intelligent decisions whether to sleep or wake according to the amount of received and stored energy. Using an adaptive strategy of this kind the amount of work can be precisely matched to the resources available to achieve maximum utilization. The paper also evaluates the performance of the proposed algorithm compared with more conventional ways of doing the same thing.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121280773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation and modeling of charging and discharging of supercapacitors 超级电容器充放电仿真与建模
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-01 DOI: 10.1109/CIRSYSSIM.2017.8023172
Sheryl Dinglasan Fenol, F. Caluyo, Jhunlyn Lorenzo
{"title":"Simulation and modeling of charging and discharging of supercapacitors","authors":"Sheryl Dinglasan Fenol, F. Caluyo, Jhunlyn Lorenzo","doi":"10.1109/CIRSYSSIM.2017.8023172","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023172","url":null,"abstract":"Supercapacitors is the new technology that can be used to replace the battery or in parallel with battery with its fast charge-discharge characteristics. Possible applications of supercapacitors are in renewable energy as sustainable energy storage and hybrid electric vehicle (HEV). This study focus on charging and discharging of supercapacitors and its behavior. Mathematical models of charging and discharging with the proposed equivalent circuits were simulated and compared with actual experiment simulation using potentiostat. The equation for approximated full discharge time of supercapacitors was also presented. Two commercially available supercapacitors with 4.7F and 3.3F capacitance and 2.5V were set-up in potentiostat using two-electrode mode.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134516412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Material handling tools for a discrete manufacturing system: A comparison of optimization and simulation 离散制造系统的物料搬运工具:优化与仿真的比较
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-01 DOI: 10.1109/CIRSYSSIM.2017.8023190
Yanting Ni, Frank Werner
{"title":"Material handling tools for a discrete manufacturing system: A comparison of optimization and simulation","authors":"Yanting Ni, Frank Werner","doi":"10.1109/CIRSYSSIM.2017.8023190","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023190","url":null,"abstract":"The improvement of the performance of material handling tools (MHTs) and the work in process (WIP) in a discrete manufacturing system have a great importance for increasing the efficiency of the production. To this end, the dynamic status of MHTs is analyzed in this paper. A Markov decision process (MDP) is used to model the MHT problems. The quantified relationships between MHTs and WIP will be discussed within the CONWIP (constant WIP) and Little's law methodologies. A dynamic programming (DP) based algorithm is developed to determine a solution for the MDP model. To reduce the computational complexity of the DP algorithm, an appropriate modification is introduced. Computational experiments are conducted in a discrete semiconductor factory and the proposed MDP+DP method is compared with simulation. The computational results show that the developed method produces rather good feasible solutions.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133152002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Realistic estimation of power penalty through a probabilistic framework in a WDM receiver with component crosstalk 具有分量串扰的WDM接收机中基于概率框架的功率惩罚的现实估计
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-01 DOI: 10.1109/CIRSYSSIM.2017.8023205
S. Sarkar, P. Mukherjee, N. Das
{"title":"Realistic estimation of power penalty through a probabilistic framework in a WDM receiver with component crosstalk","authors":"S. Sarkar, P. Mukherjee, N. Das","doi":"10.1109/CIRSYSSIM.2017.8023205","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023205","url":null,"abstract":"In this work, the performance degradation in a Wavelength Division Multiplexing (WDM) receiver system is analyzed in terms of power penalty considering the presence of multiple component crosstalk sources. In conventional way, power penalty is calculated considering the presence of all crosstalk sources simultaneously (i.e. worst case) which is not reality in practice and leads to unrealistic estimation. Here a probabilistic approach is adopted which considers all possible probabilistic appearances of the interfering channels and their realistic impact while calculating Bit Error Rate (BER) and penalty. Power penalty considering the presence of signal-crosstalk beat noise is formulated and the effect of the variation of number of interfering channels and crosstalk level are studied for a fixed thermal noise and photocurrent setting of the receiver. In addition the obtained results are compared with the existing worst case analysis model.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128627178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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