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2017 International Conference on Circuits, System and Simulation (ICCSS)最新文献

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Load forecasting via detrending and deseasoning 通过趋势和推理来预测负荷
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-08-31 DOI: 10.1109/CIRSYSSIM.2017.8023188
B. Vuksanovic, P. Martín
{"title":"Load forecasting via detrending and deseasoning","authors":"B. Vuksanovic, P. Martín","doi":"10.1109/CIRSYSSIM.2017.8023188","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023188","url":null,"abstract":"Load forecasting is a term usually applied to describe a process of estimation or prediction of future energy demand for a certain distribution grid or part of a grid. Large number of different methods and techniques used for load forecasting have been developed in the past and new and improved methods are regularly being reported in research literature. This paper describes one of traditional load forecasting approaches based on autoregressive moving average (ARMA) modelling of load demand time-series (TS). However, it reconsiders each step in this process and proposes some new procedures to improve and clarify the whole method. Effectives of described approach is demonstrated using energy consumption measurements recently recorded at substations in central London area.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128941851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low dropout regulator with temperature coefficient curvature correction topology 具有温度系数曲率校正拓扑结构的低差调节器
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023183
Nardi Utomo, S. Liter
{"title":"Low dropout regulator with temperature coefficient curvature correction topology","authors":"Nardi Utomo, S. Liter","doi":"10.1109/CIRSYSSIM.2017.8023183","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023183","url":null,"abstract":"The LDO Voltage Regulator circuit with temperature coefficient curvature correction topology is proposed in this paper. The LDO consists of a start-up circuit, a bias generator, a three-stage error amplifier, a power MOSFET, and a temperature coefficient curvature correction circuit. The circuit is simulated with 0.18μm CMOS Technology. The supply voltage can be as low as 800mV with the output voltage of 664mV. The proposed circuit obtains the temperature coefficient as low as 23.7ppm/°C for supply voltage ranging from 800mV until 1.5V. The lowest temperature coefficient of 6.1ppm/°C is obtained at 1.1V supply voltage. The temperature coefficient is measured for a wide range of temperature ranging from −50°C to 130°C. The stability is ensured from the simulation with high low-frequency open loop gain of above 105dB and high phase margin of above 100°.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123925574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance measurements for full wave inversion (FWI) based multistatic handheld ground penetrating radar (GPR) for landmine detection 基于全波反演(FWI)的多站手持式探地雷达(GPR)地雷探测性能测量
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023179
S. Sule, K. Paulson
{"title":"Performance measurements for full wave inversion (FWI) based multistatic handheld ground penetrating radar (GPR) for landmine detection","authors":"S. Sule, K. Paulson","doi":"10.1109/CIRSYSSIM.2017.8023179","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023179","url":null,"abstract":"This paper reports the results of a study to investigate the impact of antenna configuration and rough ground surface on the performance of multistatic handheld ground penetrating radar (GPR) systems for anti-personnel (AP) landmine detection. The work is a follow on to the conclusions presented in [1] which include the fact that enhanced imaging through full wave inversion (FWI) is achieved with multiple receivers in comparison to typical bistatic systems in handheld GPR. This paper seeks to address a couple of aspects of future work outlined in the aforementioned work. Specifically, the study aims to quantitatively characterise the effect of different antenna configurations and rough ground surface on the performance of small multistatic GPR systems used for FWI based subsurface imaging for demining operations. The 3D electromagnetic (EM) software CST STUDIO SUITE is used to model and simulate the GPR system and singular value decomposition (SVD) analysis is used to estimate parameter sensitivity based on the assumption of prior FWI.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128597300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A monolithic isolated gate driver using an on-chip transformer and a voltage level shifter 采用片上变压器和电压电平移位器的单片隔离栅极驱动器
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023187
Kai-Chieh Lin, Jau-Jr Lin
{"title":"A monolithic isolated gate driver using an on-chip transformer and a voltage level shifter","authors":"Kai-Chieh Lin, Jau-Jr Lin","doi":"10.1109/CIRSYSSIM.2017.8023187","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023187","url":null,"abstract":"This paper proposes a monolithic isolated gate driver design with a voltage level shifter. Incorporating voltage level converters can effectively reduce input drive voltage requirements and the overall energy needed to the power gate drivers. The on-chip transformer detailed in this study consists of a pair of on-chip inductors. Two types of the on-chip transformer structures are used: a stacked transformer (featuring higher coupling coefficient) and a tapped transformer (featuring higher voltage isolation). The on-chip transformer, full-bridge rectifier, gate driver, and voltage level converter were all produced using the TSMC 0.25-μm HV (high-voltage) CMOS process. Compared to the ündings of the previous study, simulations conducted in this study showed that the proposed monolithic isolated gate driver with a voltage level shifter required a 62% lower power input voltage and 34% less power consumption. Moreover, it could provide 12 V of output voltage and drive a load of 6000 pF with the rise and fall time less than 1 μs.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132926945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The design of optimal phase tracking current controlled attenuators 最佳相位跟踪电流控制衰减器的设计
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023184
A. Stofberg, P. Van Der Walt, J. B. de Swardt
{"title":"The design of optimal phase tracking current controlled attenuators","authors":"A. Stofberg, P. Van Der Walt, J. B. de Swardt","doi":"10.1109/CIRSYSSIM.2017.8023184","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023184","url":null,"abstract":"Multi-channel receivers often require good phase tracking between channels. If a PIN diode current controlled attenuator (CCA) is needed in each channel, the individual CCAs should track in phase over the full control range. Variations in PIN diode complex impedance as well as component tolerances will cause phase tracking errors in a family of CCAs. A method to compare CCA topologies in terms of phase tracking performance is developed. By using sensitivity analysis and defining a single root sum square measure for comparing attenuator topologies, an optimum topology is identified for implementing an electronically controlled variable attenuator. The results clearly show that the cascade parallel quarter-wave attenuator topology will have the smallest phase tracking error within a family of CCAs.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123837627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research and design of multi sets of magnetic switches wound on one magnetic ring: Application of magnetic switch in pulsed power device 多组磁开关绕在一个磁环上的研究与设计:磁开关在脉冲功率器件中的应用
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023170
L. Rong, Q. Rong
{"title":"Research and design of multi sets of magnetic switches wound on one magnetic ring: Application of magnetic switch in pulsed power device","authors":"L. Rong, Q. Rong","doi":"10.1109/CIRSYSSIM.2017.8023170","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023170","url":null,"abstract":"A technical scheme which the two sets of windings wound on a magnetic ring composed of two sets of magnetic switches is proposed. And on this basis, a scheme of PFL-MARX (pulse forming line MARX generator) circuit is proposed. In this paper, according to the electromagnetic theory and formula derivation, it can be obtained that the magnetizing inductance, saturated inductance, the time of magnetic saturation from unsaturated to saturated have nothing to do with the current number, that is to say, have nothing to do with the number of symmetrical windings wound on the magnetic ring. The conclusion is verified by simulation in the software environment of Maxwell Ansoft. The simulation results show that the theory deduction is correct. In the PSPICE, the model of the pulse compression circuit and the voltage-multiplying circuit is build, and simulation is carried out. The results demonstrate that the scheme is feasible, and it can also play the effect of voltage-multiplying. The implementation of such a scheme can greatly reduce the volume and weight of the pulsed power device.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130932714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficiency improvement of dual mode DC-DC buck converter under light load using PTWS with a zero current detector 利用带零电流检测器的PTWS提高轻载双模DC-DC降压变换器的效率
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023185
Y. Shin, Hak-Yun Kim, Jin-won Kim, Seong-Yeol Choi, Yeong-Seuk Kim, Ho-Yong Choi
{"title":"Efficiency improvement of dual mode DC-DC buck converter under light load using PTWS with a zero current detector","authors":"Y. Shin, Hak-Yun Kim, Jin-won Kim, Seong-Yeol Choi, Yeong-Seuk Kim, Ho-Yong Choi","doi":"10.1109/CIRSYSSIM.2017.8023185","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023185","url":null,"abstract":"This paper presents a dual-mode DC-DC buck converter using power transistor width scaling (PTWS) with a zero current detector to improve power efficiency under light load. The buck converter is operated in a dual mode, combining the switching frequency modulation (SFM) mode which uses the voltage controlled oscillator (VCO) under light load, with the PWM mode for heavy load. To enhance power efficiency under light load a PTWS scheme is employed, in which the inductor current is detected using a zero current detector (ZCD) and then used to select the gate size of the power switching transistor. The proposed circuit was designed using a Magnachip 0.35μm CMOS process. Simulation results shows that our proposed converter has 81.3% ∼ 93% power efficiency for output load currents of 10mA ∼ 250mA, which is a 5.3% improvement compared to a simple SFM-PWM dual mode and an 8.9% improvement compared to a PWM-only mode under a light load of 10mA, respectively.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127721945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An investigation of energy efficiency in 5G wireless networks 5G无线网络能效研究
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023199
S. Rizvi, A. Aziz, Muhammad Taha Jilani, N. Armi, Ghulam Muhammad, Shujaat Hussain Butt
{"title":"An investigation of energy efficiency in 5G wireless networks","authors":"S. Rizvi, A. Aziz, Muhammad Taha Jilani, N. Armi, Ghulam Muhammad, Shujaat Hussain Butt","doi":"10.1109/CIRSYSSIM.2017.8023199","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023199","url":null,"abstract":"In next generation wireless networks along with the overwhelming demand of high data rate and network capacity, the user demands ubiquitous connectivity with the network. In order to fulfill the demand of anywhere at any time data services, the network operators have to install more and more base stations that eventually leads towards high power consumption. For this, the potential solution is derived from 5G network that proposes a heterogeneous environment of wireless access networks. More particularly, deployment of Femto and Pico cell under the umbrella of Macro cell base stations (BS). Such networking strategy will result high network capacity and energy efficiency along with better network coverage. In this article, an analysis of energy efficiency has been carried out by using two-tier and three tier network configurations. The simulation results demonstrate that rational deployment of small cells improves the energy efficiency of wireless network.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126680485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A flash assisted dynamic range segmented successive approximation register (SAR) analog to digital converter 一种闪光辅助动态范围分段逐次逼近寄存器(SAR)模数转换器
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023178
Sounak Roy, Raju Naik, Archana Kumari, D. Mahesh
{"title":"A flash assisted dynamic range segmented successive approximation register (SAR) analog to digital converter","authors":"Sounak Roy, Raju Naik, Archana Kumari, D. Mahesh","doi":"10.1109/CIRSYSSIM.2017.8023178","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023178","url":null,"abstract":"A new SAR ADC design is presented in this paper, which applies a flash ADC for the segmentation of its dynamic range. An n bit flash component of the proposed ADC divides the dynamic range into 2n segments. Each of these segments are further resolved by finer SAR ADCs. Application of the n-bit flash ADC reduces n execution cycles of the SAR ADC, thus enhancing the sampling rate. Hardware addition costs nominal power overhead, which helps to improve the figure-of-merit (FoM) significantly. Two SAR ADCs using the proposed technique are designed and simulated in a 180 nm CMOS process. 6-bit and 7-bit ADCs with the proposed design produce signal-to-noise-and-distortion ratio (SNDR) of 32.42 dB and 38.07 dB respectively. FoM of 6-bit and 7-bit proposed ADCs are 0.54 and 0.38 fraction of their conventional counterparts respectively.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126599098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
DC biased input stage with differential photocurrent sensing for VLC front-ends 直流偏置输入级与差分光电流传感VLC前端
2017 International Conference on Circuits, System and Simulation (ICCSS) Pub Date : 2017-07-14 DOI: 10.1109/CIRSYSSIM.2017.8023204
M. Basha, R. Binns
{"title":"DC biased input stage with differential photocurrent sensing for VLC front-ends","authors":"M. Basha, R. Binns","doi":"10.1109/CIRSYSSIM.2017.8023204","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2017.8023204","url":null,"abstract":"The reverse bias voltage across the PIN photodiode is essential for the photodiode to operate in the photoconductive mode. This paper presents an input bias stage with differential photocurrent sensing for VLC front-ends. The bias voltage is provided from within the transimpedance amplifier's (TIA) circuit eliminating the need of external bias voltage. The amount of bias voltage could be optimised according to the photodiode required sensitivity and capacitance. The differential configuration makes the TIA immune to any common mode noise. The proposed method is applied to a hypothetical TIA and results are compared with single ended structure. Simulation results showed that using this approach it is possible to achieve a transimpedance gain of 120 dBΩ over a maximum bandwidth of 14.5 MHz with a common mode rejection ratio of 61 dB while the circuit provides a controlled bias voltage of up to 6 V across the PIN photodiode eliminating the need for external bias voltage source.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134532698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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