A flash assisted dynamic range segmented successive approximation register (SAR) analog to digital converter

A new SAR ADC design is presented in this paper, which applies a flash ADC for the segmentation of its dynamic range. An n bit flash component of the proposed ADC divides the dynamic range into 2n segments. Each of these segments are further resolved by finer SAR ADCs. Application of the n-bit flash ADC reduces n execution cycles of the SAR ADC, thus enhancing the sampling rate. Hardware addition costs nominal power overhead, which helps to improve the figure-of-merit (FoM) significantly. Two SAR ADCs using the proposed technique are designed and simulated in a 180 nm CMOS process. 6-bit and 7-bit ADCs with the proposed design produce signal-to-noise-and-distortion ratio (SNDR) of 32.42 dB and 38.07 dB respectively. FoM of 6-bit and 7-bit proposed ADCs are 0.54 and 0.38 fraction of their conventional counterparts respectively.