A high-performance branch predictor design considering memory capacity limitations

Abstract

Pipeline flush due to the flow change of instruction can be a huge degradation factor in modern processors since the branch instructions consist of more than 20 % of all instructions when running a program. However, with a characteristic called branch locality, the result of branch execution is predictable. By utilizing branch locality, there have been a lot of researches to improve the prediction rate of branch predictor however, most of these did not consider the memory capacity so that they cannot be implemented to the embedded systems. Therefore, we propose a new scheme with high prediction rate while maintaining low memory consumption. The new scheme uses an XOR gate to diversify the Pattern History Table (PHT) index. However, the last 6 bits of the index are replaced with PC addresses to enhance the distinction ability of branch instruction addresses. The simulation was executed using SimpleScalar 3.0 simulator, and benchmarks from SPEC CPU2000. Based on the simulation result, this new structure achieved higher prediction rate while maintaining the low memory consumption. Consequently, the new scheme is the most appropriate branch predictor among comparison group presented in this paper.