A scheme of synchronization calibration between high-speed acquisition boards

Abstract

In high-speed acquisition system, timing sequence of sampling gate signal and SYNC reset signal may affect synchronization between high-speed acquisition boards (called board synchronization). The problem of board synchronization can be solved by delaying these two signals. In order to ensure board synchronization, a scheme was proposed to estimate reasons for abnormal synchronization according to the difference between boards and calibrated delay parameters of sampling gate signal and SYNC reset signal. When the difference between boards was m sampling points (m is sampling frequency dividing ratio), the abnormal synchronization was caused by sampling gate signal. When the difference between boards was 1 sampling point, the abnormal synchronization was caused by SYNC reset signal. It was effective to adjust the delay parameter of sampling gate signal and the delay parameter of SYNC reset signal to ensure board synchronization. Through test, board synchronization deviation was not more than 20ps. This scheme does not need ergodic calibration of all delay parameters, largely increases efficiency.