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Noise Reduction in LNAs Using a Conductive Path to Ground Technique in SiGe Technology 利用SiGe技术中的导电路径到地技术降低LNAs中的噪声
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251696
J. Alvarado, J. Duster, K. Kornegay
{"title":"Noise Reduction in LNAs Using a Conductive Path to Ground Technique in SiGe Technology","authors":"J. Alvarado, J. Duster, K. Kornegay","doi":"10.1109/ASSCC.2005.251696","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251696","url":null,"abstract":"A passive noise suppression technique was implemented on a family of monolithic low-noise amplifiers using a 0.5mum SiGe BiCMOS process with 47GHz fT transistors. This method provides the entire circuit with a conductive path to ground the P-substrate. Near active device regions, noise injection and crosstalk paths are shunted to ground. This technique decreased the LNAs noise figures by 1.88dB, 0.34dB, and 0.82dB at 5.25GHz, 2.45GHz, and 2.14GHz respectively. While DC power consumption is reduced, the gain improved by 5.3dB and 2.5dB at 5.25GHz and 2.14GHz respectively","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123098901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Energy-Efficient Optimization of the Viterbi ACS Unit Architecture Viterbi ACS机组结构的节能优化
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251708
H. Dao, B. Zeydel, V. Oklobdzija
{"title":"Energy-Efficient Optimization of the Viterbi ACS Unit Architecture","authors":"H. Dao, B. Zeydel, V. Oklobdzija","doi":"10.1109/ASSCC.2005.251708","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251708","url":null,"abstract":"Different architectural approaches for saving energy are considered for the ACS unit of a Viterbi decoder. It was found that although providing less throughput improvement than parallelism, pipelining is more energy efficient. The optimal mix of these two architectures favors more pipelining at lower throughput requirements","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131983894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Wireless LAN Baseband LSI for High-Definition A/V Content Transmission 一种用于高清A/V内容传输的无线局域网基带LSI
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251780
H. Nakakita, N. Kato, T. Wakutsu, Y. Miyamoto, A. Yamaga, S. Kaburaki, M. Sekiya, T. Kamimura, K. Matsue, K. Tsuchie, K. Horisaki, T. Shiozawa, D. Taki, H. Kajihara, T. Aono, T. Shimada, T. Fujisawa, T. Ueno, K. Shimizu, M. Ikuta, S. Yamazaki, M. Kuwahara, M. Namekata, T. Saito, Y. Unekawa
{"title":"A Wireless LAN Baseband LSI for High-Definition A/V Content Transmission","authors":"H. Nakakita, N. Kato, T. Wakutsu, Y. Miyamoto, A. Yamaga, S. Kaburaki, M. Sekiya, T. Kamimura, K. Matsue, K. Tsuchie, K. Horisaki, T. Shiozawa, D. Taki, H. Kajihara, T. Aono, T. Shimada, T. Fujisawa, T. Ueno, K. Shimizu, M. Ikuta, S. Yamazaki, M. Kuwahara, M. Namekata, T. Saito, Y. Unekawa","doi":"10.1109/ASSCC.2005.251780","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251780","url":null,"abstract":"This paper presents the first wireless LAN baseband LSI capable of transmitting high-definition audio with video (HD-A/V) content requiring secure content protection. The LSI fully complies with IEEE 802.11a, e, h, and i. The hybrid coordination function controlled channel access (HCCA) of 802.11e is employed to reserve the transmission period for HD-A/V content. In addition, the block acknowledgement of 802.11e with a forward error correction mechanism is introduced to increase the throughput. Moreover, the digital transmission content protection over the Internet protocol (DTCP-IP) is implemented to prohibit casual copying. High availability of this LSI is provided by two kinds of host interfaces (PCI-bus and HC-bus), an MPEG-2 transport stream interface, and a digital beam forming LSI interface","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134156428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 900 MHz CMOS RF Direct Conversion Receiver Front-end with 3-dB NF and 30-KHz 1/f Noise Corner 具有3db NF和30khz 1/f噪声角的900mhz CMOS射频直接转换接收机前端
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251737
Trung‐Kien Nguyen, Sang-Gug Lee, D. Kang
{"title":"A 900 MHz CMOS RF Direct Conversion Receiver Front-end with 3-dB NF and 30-KHz 1/f Noise Corner","authors":"Trung‐Kien Nguyen, Sang-Gug Lee, D. Kang","doi":"10.1109/ASSCC.2005.251737","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251737","url":null,"abstract":"A low-power, low 1/f noise RF receiver front-end for 900 MHz IEEE 802.15.4 ZigBee standard in 0.18 mum CMOS technology is implemented. In combination with LNA, a passive mixer showing excellent 1/f noise is adopted. The measured results show the conversion gain of 30 dB, NF of 3 dB with 1/f noise corner frequency of 30 KHz. Two-tone test measurements indicate -5 dBm IIP3, +45 dBm IIP2. The RF receiver front-end dissipates 2 mA from 1.8 V supply","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133570404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Measurements of Digital Signal Delay Variation Due to Dynamic Power Supply Noise 动态电源噪声下数字信号延迟变化的测量
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251691
M. Fukazawa, M. Nagata
{"title":"Measurements of Digital Signal Delay Variation Due to Dynamic Power Supply Noise","authors":"M. Fukazawa, M. Nagata","doi":"10.1109/ASSCC.2005.251691","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251691","url":null,"abstract":"On-chip 100-ps/100-muV waveform accurate measurements on signal transition in a large-scale digital circuits clearly demonstrate the correlation of dynamic delay variation with power supply noise waveforms. An approximately linear dependence of delay increase with drop height holds under the existence of static IR drop, however, the coefficient of delay increase is strongly influenced by a dynamic power supply noise waveform. Another cause of delay variation is found as a distortion of signal waveforms during logic transition by dynamic power supply noise, where the process is sensitive not only to a noise waveform but also to a relative time difference among victim and aggressor pairs, which can be generally found in a design with multiple clock domains","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116663189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
The Power Conscious Synergistic Processor Element of a Cell Processor 单元处理机的功率意识协同处理机元件
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251779
O. Takahashi, S. Cottier, S. Dhong, B. Flachs, K. Hirairi, H. Peter Hofstee, B. Michael, H. Noro, D. Wendel, M. White
{"title":"The Power Conscious Synergistic Processor Element of a Cell Processor","authors":"O. Takahashi, S. Cottier, S. Dhong, B. Flachs, K. Hirairi, H. Peter Hofstee, B. Michael, H. Noro, D. Wendel, M. White","doi":"10.1109/ASSCC.2005.251779","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251779","url":null,"abstract":"A 4-way SIMD streaming processor of a cell processor is developed in a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the non-SRAM area. ISA, microarchitecture, and physical implementation are co-optimized to achieve a compact and power efficient design","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114785400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Realization of Trans-impedance Amplifier for Particle Counting Chip 粒子计数芯片跨阻抗放大器的实现
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251816
Jung-Tang Huang, Hsin-Nan Chen
{"title":"Realization of Trans-impedance Amplifier for Particle Counting Chip","authors":"Jung-Tang Huang, Hsin-Nan Chen","doi":"10.1109/ASSCC.2005.251816","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251816","url":null,"abstract":"MEMS (micro electro mechanical systems) technology could be applied on bio-chips to measure and detect micro objects. Generally, the detected signal is so small that we need to amplify it for next processing (such as A/D converter). In this study, we develop a trans-impedance amplifier (TIA) circuit to detect the blocking conductance when particles across an ion-pore. Consider the simple circuits, simple manufacture process, and the capability of integrating with MEMS process. The TIA circuit and the MEMS ion-pore is designed based on 0.35mum CMOS process. The measured results of this amplifier are 94dBOmega high gain, low noise as the M.D.S. of 25nA, and the bandwidth larger than 15MHz","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115561134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Single-Chip Dual-Band 0.25μm CMOS Transceiver for 802.11a/b/g Wireless LAN 一种用于802.11a/b/g无线局域网的单芯片双带0.25μm CMOS收发器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251715
M. Kuo, Yi-Bin Lee, Shiau-Wen Kao, Chih-Hung Chen, Chun-Lin Ko, Tzu-Yi Yang
{"title":"A Single-Chip Dual-Band 0.25μm CMOS Transceiver for 802.11a/b/g Wireless LAN","authors":"M. Kuo, Yi-Bin Lee, Shiau-Wen Kao, Chih-Hung Chen, Chun-Lin Ko, Tzu-Yi Yang","doi":"10.1109/ASSCC.2005.251715","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251715","url":null,"abstract":"This paper presents a dual-band, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, transceiver for IEEE 802.11a/b/g standards in a 0.25mum CMOS process. With a novel architecture and frequency planning, only one voltage-controlled oscillator and frequency synthesizer is required to perform frequency transferring for dual-band operation, and the building blocks of both receiver and transmitter could be shared as many as possible. The fully integrated VCO and frequency synthesizer centered at 3.8GHz achieves an integrated phase noise of 1.35deg rms. The transmitter achieves -33dB EVM at -3dBm output power, and -29dB EVM at -7dBm output power from the integrated preamplifier for 2.4GHz and 5GHz bands respectively. The receiver also exhibits a noise figure of 3dB at 2.4GHz band and 3.8dB at 5GHz band. The transceiver occupies an area of 25mm2","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"87 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131177102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Networks-on-chip and Networks-in-Package for High-Performance SoC Platforms 面向高性能SoC平台的片上网络和封装网络
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251783
Kangmin Lee, Se-Joong Lee, Donghyun Kim, Kwanho Kim, Gawon Kim, Joungho Kim, H. Yoo
{"title":"Networks-on-chip and Networks-in-Package for High-Performance SoC Platforms","authors":"Kangmin Lee, Se-Joong Lee, Donghyun Kim, Kwanho Kim, Gawon Kim, Joungho Kim, H. Yoo","doi":"10.1109/ASSCC.2005.251783","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251783","url":null,"abstract":"A structured packet-switched networks-on-chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform. The chip integrates multiprocessors, multiple memories, and other heterogeneous intellectual properties and interconnection with 51mW and 1.6GHz on-chip networks. The NoC adopts a partial activated crossbar, low-energy coding, and low-swing signaling for the power consumption optimization. A network-in-package integrating four NoCs is fabricated in a 676-BGA-type package for larger and scalable systems and demonstrates 2D-image-processing and 3D-graphics applications","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"57 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129472559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Practical Synthesis of 13-bit 40-MSample/s Pipelined ADC 13-bit 40-MSample/s流水线ADC的实用合成
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251809
Y. Chien, G. Ma, T. Mukherjee
{"title":"Practical Synthesis of 13-bit 40-MSample/s Pipelined ADC","authors":"Y. Chien, G. Ma, T. Mukherjee","doi":"10.1109/ASSCC.2005.251809","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251809","url":null,"abstract":"A 13-bit pipelined ADC achieving 67 dB SNDR without digital calibration while consuming 313mW @ 3.3V 40 MSPS is designed using analog synthesis tools. The MDACs in the pipeline have identical topology and can be synthesized to optimize pipeline performance in less than I day. Figure of merit of the three test keys comparing a manually designed, partially synthesized, and fully synthesized ADC is reported showing the efficacy and efficiency of the proposed approach","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128403604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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