发布求助
文献互助 智能选刊 最新文献

2005 IEEE Asian Solid-State Circuits Conference最新文献

筛选
英文 中文
A Low-Power and Compact Analog CMOS Processing Chip for Portable ECG Recorders 一种用于便携式心电记录仪的低功耗紧凑型模拟CMOS处理芯片
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251768
M. Shojaei-Baghini, R. Lal, Dinesh K. Sharma
{"title":"A Low-Power and Compact Analog CMOS Processing Chip for Portable ECG Recorders","authors":"M. Shojaei-Baghini, R. Lal, Dinesh K. Sharma","doi":"10.1109/ASSCC.2005.251768","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251768","url":null,"abstract":"This paper presents a three-channel low-power and compact analog processor including a test chip, fabricated in TSMC 0.35mum mixed-mode CMOS process, for portable electrocardiogram (ECG) monitoring devices. The chip highlights integrating CMOS instrumentation amplifiers based on current balancing technique to implement more analog signal conditioning functions at instrumentation amplifiers. First order low-pass filtering as well as programmable high-pass filtering has been included in each instrumentation amplifier. Experimental results show that each channel draws 22muA from a 3.3V battery. Measurement results satisfy recommended specifications for portable ECG recorders. The programmable test board designed using the chip, records three-leads ECG with frontal plane and precordial leads. Analog signal conditioning circuit, measurement results and recorded ECGs are given in this paper","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123166198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
A Wide-band Low Noise Quadrature CMOS VCO 一种宽带低噪声正交CMOS压控振荡器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251731
Yi-Hsien Cho, Ming-Da Tsai, Ying-Tang Chang, Huei Wang
{"title":"A Wide-band Low Noise Quadrature CMOS VCO","authors":"Yi-Hsien Cho, Ming-Da Tsai, Ying-Tang Chang, Huei Wang","doi":"10.1109/ASSCC.2005.251731","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251731","url":null,"abstract":"A wide tuning range and low noise CMOS quadrature voltage-controlled oscillator (QVCO) using 0.18-mum 1P6M standard CMOS process is proposed in this paper. The VCO is realized employing switchable capacitors, so as to work in dual band and increase operation frequency. Moreover, the dual band operation could decrease the tuning sensitivity in each band and hence lower the phase noise. The VCO operates from 5.14 to 6.3 GHz with more than 20% tuning range. The measured phase noise at 1-MHz offset is -120.2 dBc/Hz at 5.5 GHz with VCO cores drawing total current of 8 mA at 1.8 V supply and the output power is about 1.5 dBm","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131269768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design 无最坏情况下低压SoC的片上PVT控制系统
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251728
T. Gyohten, F. Morishita, M. Okamoto, K. Dosaka, K. Arimoto
{"title":"An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design","authors":"T. Gyohten, F. Morishita, M. Okamoto, K. Dosaka, K. Arimoto","doi":"10.1109/ASSCC.2005.251728","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251728","url":null,"abstract":"In this paper, we propose on-chip PVT (process, voltage, and temperature) control system for worst-caseless lower voltage SoC design that consist of the adaptive voltage management (AVM). The proposed AVM accurately controls to set the most suitable voltage level with table look-up method. This PVT control system realizes wide operating margin, DFM function for low voltage SoC. The experimental chip is fabricated on 90nm CMOS process and confirmed the proposed architecture accurately controls the voltage level and the operation margin securing at the lower voltage","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117352489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 6-Gbps/pin Half-Duplex LVDS I/O for High-Speed Mobile DRAM 用于高速移动DRAM的6 gbps /引脚半双工LVDS I/O
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251805
Sua Kim, Bae-Sun Kong, Chil-gi Lee, Jin-Hyun Kim, Woo-Seop Kim, Young-Hyun Jun, Changhyun Kim
{"title":"A 6-Gbps/pin Half-Duplex LVDS I/O for High-Speed Mobile DRAM","authors":"Sua Kim, Bae-Sun Kong, Chil-gi Lee, Jin-Hyun Kim, Woo-Seop Kim, Young-Hyun Jun, Changhyun Kim","doi":"10.1109/ASSCC.2005.251805","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251805","url":null,"abstract":"This paper presents a high-speed LVDS I/O interface for mobile DRAMs. A data rate of 6Gbps/pin and a transmit-jitter of 57.31ps pk-pk were demonstrated, in which an 800MHz clock and a 200mV swing were used. The power consumption by I/O circuit is 6.2mW/pin when a 10pf load is connected to the I/O, and output supply voltage is 1.2V. The proposed mobile DRAM has 6 data pins and 4 address/command pins for a multi-chip package (MCP). The transmitter uses a feed-back LVDS output driver and a common-mode feed-back controller achieving the reduction of driver currents and the constant common-mode as half voltage level. To achieve a low-transmit jitter, we use a driver with a double step pre-emphasis. The receiver employs a shared preamplifier scheme, which ensures transmit power reduction. The proposed DRAM with LVDS I/O was fabricated using an 80-nm DRAM process. It exhibits 161.1mV times 150ps rms eye-windows on the given channel","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125871866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design of a Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate 基于浮动门- mos功能通闸的多上下文FPGA设计
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251755
M. Hariyama, S. Ogata, M. Kameyama, Y. Morita
{"title":"Design of a Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate","authors":"M. Hariyama, S. Ogata, M. Kameyama, Y. Morita","doi":"10.1109/ASSCC.2005.251755","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251755","url":null,"abstract":"Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained MC-FPGA architecture using a floating-gate-MOS functional pass gate (FGFP) is presented which merges threshold operation and storage function on a single floating-gate MOS transistor. The transistor count of the proposed multi-context switch (MC-switch) is reduced to 10% in comparison with SRAM-based one. The transistor count of the proposed MC-switch is also reduced to 20% in comparison with the MC-switch that uses floating-gate MOS transistors just as storage device. The test chip is designed using a 0.35mum EPROM technology, and the area of the proposed MC-FPGA is reduced to about 50% of that of a conventional MC-FPGA","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125988522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SiGe HBT based 24-GHz LNA and VCO for Short-Range Ultra-Wideband Radar Systems 基于SiGe HBT的24ghz LNA和VCO短距离超宽带雷达系统
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251756
T. Masuda, T. Nakamura, M. Tanabe, N. Shiramizu, S. Wada, T. Hashimoto, K. Washio
{"title":"SiGe HBT based 24-GHz LNA and VCO for Short-Range Ultra-Wideband Radar Systems","authors":"T. Masuda, T. Nakamura, M. Tanabe, N. Shiramizu, S. Wada, T. Hashimoto, K. Washio","doi":"10.1109/ASSCC.2005.251756","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251756","url":null,"abstract":"24-GHz low noise amplifier (LNA) and voltage controlled oscillator (VCO) in 0.25-mum SiGe BiCMOS technology were developed to create low-cost radio frequency (RF) modules for short-range ultra-wideband radar systems. A two-stage shunt-feedback LNA that used inductive biasing had a -3-dB bandwidth of 11.4 GHz, a noise figure of 3.8 dB at 24 GHz, and a group delay deviation within 21 ps (from 10 GHz to 30 GHz). The LC-tuned differential VCO, with a high quality-factor center-tapped inductor design, oscillated at 24 GHz with phase noise of -100 dBc/Hz at 1 MHz offset. The VCO core consumed only 2 mA of current","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"58 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114035962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Design of a High-Performance Switch for Circuit-Switched On-Chip Networks 一种用于电路交换片上网络的高性能交换机设计
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251770
Chia-Ming Wu, Hsin-Chou Chi
{"title":"Design of a High-Performance Switch for Circuit-Switched On-Chip Networks","authors":"Chia-Ming Wu, Hsin-Chou Chi","doi":"10.1109/ASSCC.2005.251770","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251770","url":null,"abstract":"System-on-a-chip (SoC) designs provide designers to integrate dozens of heterogeneous IP blocks together by a dedicated interconnect network. The major problems in the ultra deep sub-micron technology SoC design arise from the interconnection networks, such as non-scalable global wire delay, failure to achieve global synchronization, and errors due to signal integrity issues. These problems might be mitigated by the network-on-chip (NoC) approach based on regular on-chip communication networks. In this paper, the authors propose the pre-scheduled circuit-switched network for NoC architectures. The authors have designed the switch supporting the network. Such architectures based on circuit switching with efficient buffer management can achieve guaranteed transmission latencies","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131536707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Dual-Bias Power Amplifier Designs for WLAN Applications WLAN应用的双偏置功率放大器设计
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251746
Chien-Chang Huang, Wei-Ting Chen
{"title":"Dual-Bias Power Amplifier Designs for WLAN Applications","authors":"Chien-Chang Huang, Wei-Ting Chen","doi":"10.1109/ASSCC.2005.251746","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251746","url":null,"abstract":"This paper presents the power amplifier (PA) design for IEEE 802.11g WLAN applications by using InGaP/GaAs heterojunction bipolar transistors (HBT) with the dual bias network as the linearizer to improve the output power capability and linearity. The final designed PA utilizes 3.3 V supply voltage producing the maximum power-aided-efficiency (PAE) in 42.8% with 25.5 dBm output power and 18 dB in gain for a 2.4 GHz single-tone stimulus. The measured performances under WLAN modulation signal excitation are 23 dBm output power and 31.5% of PAE with the adjacent-power-ratio (ACPR) less then -20 dBc, satisfying the specifications of the standard","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132362478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Personal-Use Single-Chip Emulator Using Dynamically Reconfigurable Logic Array 一种基于动态可重构逻辑阵列的个人用单片机仿真器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251732
K. Kotani, N. Miyamoto, T. Ohkawa, A. Jamak, S. Kita, T. Ohmi
{"title":"A Personal-Use Single-Chip Emulator Using Dynamically Reconfigurable Logic Array","authors":"K. Kotani, N. Miyamoto, T. Ohkawa, A. Jamak, S. Kita, T. Ohmi","doi":"10.1109/ASSCC.2005.251732","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251732","url":null,"abstract":"A personal-use single-chip emulation system using a dynamically reconfigurable logic array named flexible processor II (FP2) has been developed. It can emulate large target circuit by sequential execution of sub-circuits divided from the target circuit. The size of the target circuit for emulation is theoretically unlimited. In order to realize such features, FP2 is equipped with temporal communication module (TCM) and flexible logic element (FLE), which are essential for handling temporal data communication between divided sub-circuits and for reducing the amount of configuration data, respectively. A place-and-route tool for FP2 named PELOC, which takes care of sequential execution of divided sub-circuits and carries out the temporal partitioning, spatial partitioning, placement, routing and configuration data generation has also been developed. We have developed a single-chip emulation system on a printed circuit board and confirmed that its emulation speed is several hundred times faster than that of Verilog simulator and in some cases also faster than a conventional emulator using lots of parallel-connected FPGAs","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133487287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Low-Phase-Noise Low-Phase-Error 2.4GHz CMOS Quadrature VCO 低相位噪声低相位误差2.4GHz CMOS正交压控振荡器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251720
Jung-Yu Chang, Chia-Hsin Wu, Shen-Iuan Liu
{"title":"A Low-Phase-Noise Low-Phase-Error 2.4GHz CMOS Quadrature VCO","authors":"Jung-Yu Chang, Chia-Hsin Wu, Shen-Iuan Liu","doi":"10.1109/ASSCC.2005.251720","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251720","url":null,"abstract":"A 2.4GHz low-phase-noise and low-phase-error LC tank quadrature voltage controlled oscillator (QVCO) using the parasitic vertical BJT coupling and RC phase shifters is presented. Based on the proposed techniques, the proposed QVCO can simultaneously have low phase noise and low phase error. This QVCO circuit has been realized in a 0.18mum triple-well CMOS process and exhibits below 0.2deg phase error with phase noise of -105dBc/Hz at 100kHz offset frequency . The tuning range is 380MHz from 2.27GHz to 2.65GHz with control voltage from 0.3V to 1.8V. It consumes 5.4mW at each tank","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134254392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书