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A Multimode GSM/DCS/WCDMA Double Loop Frequency Synthesizer 多模GSM/DCS/WCDMA双回路频率合成器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251700
Franck Badets, Laurent Camino, S. Dedieu, D. Belot, Sébastien Rieubon, Thiery Divel, Patrick Cerisier
{"title":"A Multimode GSM/DCS/WCDMA Double Loop Frequency Synthesizer","authors":"Franck Badets, Laurent Camino, S. Dedieu, D. Belot, Sébastien Rieubon, Thiery Divel, Patrick Cerisier","doi":"10.1109/ASSCC.2005.251700","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251700","url":null,"abstract":"In this paper a WCDMA/GSM/DCS/PCS multimode frequency synthesizer is presented. It consists in a double loop synthesizer with a programmable divider between each integer synthesizer in order to provide fractional steps. The synthesizer has been implemented in a STMicroelectronics 0.25 mum RF BiCMOS technology. Measured phase noise at 400 kHz of the 3.8 GHz carrier is -118 dBc/Hz. Power consumption is about 21 mA from a 2.5 V battery","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115387019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 1-V 27mW 10-GHz LC-NOR-Ring QVCO for UWB-OFDM Direct Frequency Synthesizer 用于UWB-OFDM直接频率合成器的1v 27mW 10ghz lc - no - ring QVCO
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251759
Chien-Chih Lin, Chorng-Kuang Wang
{"title":"A 1-V 27mW 10-GHz LC-NOR-Ring QVCO for UWB-OFDM Direct Frequency Synthesizer","authors":"Chien-Chih Lin, Chorng-Kuang Wang","doi":"10.1109/ASSCC.2005.251759","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251759","url":null,"abstract":"This paper proposes an LC-NOR-ring quadrature voltage controlled oscillator (QVCO). Applied to the direct frequency synthesizer used in the frequency-hopped MB-OFDM UWB system, the ring is designed to enhance quadrature phase accuracy. To prevent from the inactive equilibrium state in an even-numbered delay-stage ring, the QVCO comprises four stages of NMOS-NOR gates that stimulate oscillation and equip with low-voltage operation capability. Inductor loads are used in accompany with the varactors to reduce the power consumption. Realized in a 0.18-mum 1P6M CMOS process, the circuit draws 27-mA current from a 1-V supply. The core circuit occupies an area of 1.012 times 0.35mm2 . The measured oscillation frequency shows that the QVCO has the range of 9.7GHz to 10.6GHz. The phase noise performance is above -90dBc/Hz from 10-kHz offset in the wideband sense","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127354737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
10GBase-LX CMOS Automatic Gain Control Amplifier Design 10GBase-LX CMOS自动增益控制放大器设计
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251788
I-Hsin Wang, Wei-Sheng Chen, Shen-Iuan Liu
{"title":"10GBase-LX CMOS Automatic Gain Control Amplifier Design","authors":"I-Hsin Wang, Wei-Sheng Chen, Shen-Iuan Liu","doi":"10.1109/ASSCC.2005.251788","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251788","url":null,"abstract":"A 5Gbps automatic gain control amplifier is presented with 27.8dB input dynamic range for 10GBase-LX4 Ethernet in 0.18mum CMOS technology. Five push-pull inverters use self-bias resistors and inductive-series peaking technique to realize a variable gain amplifier (VGA). This VGA achieves 4GHz bandwidth and 20dB linear-in-dB gain tuning range. The proposed 5Gbps AGC amplifier yields constant output amplitude 100mV for an input 27.8dB dynamic range","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125391158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping 采用之字形功率门控、双vth /VDD和micro -VDD跳频的95%减漏FPGA
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251687
C. Q. Tran, H. Kawaguchi, T. Sakurai
{"title":"95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping","authors":"C. Q. Tran, H. Kawaguchi, T. Sakurai","doi":"10.1109/ASSCC.2005.251687","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251687","url":null,"abstract":"Low-power FPGA architecture is proposed based on fine-grained V <sub>DD</sub> control scheme called micro-V<sub>DD</sub>-hopping. Four configurable logic blocks (CLB) are grouped into one block where V<sub>DD</sub> is shared. In the micro-V<sub>DD</sub>-hopping scheme, V <sub>DD</sub> of each block is varied between the higher V<sub>DD</sub> (V<sub>DDH</sub>) and the lower V<sub>DD</sub> (V<sub>DDL</sub>) spatially and temporally to achieve lower power, while keeping performance undegraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. The proposed FPGA is fabricated using 035mum CMOS technology together with the conventional fixed-V<sub>DD</sub> FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the highest speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGA is 2%","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129559897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
VDD-Hopping Accelerator for On-Chip Power Supplies Achieving Nano-Second Order Transient Time 实现纳秒级瞬态时间的片上电源vdd跳频加速器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251686
K. Onizuka, T. Sakurai
{"title":"VDD-Hopping Accelerator for On-Chip Power Supplies Achieving Nano-Second Order Transient Time","authors":"K. Onizuka, T. Sakurai","doi":"10.1109/ASSCC.2005.251686","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251686","url":null,"abstract":"A VDD-hopping accelerator for on-chip power supply circuits is proposed and the effectiveness of the accelerator circuit is experimentally verified. The circuit enables nano-second order transient time in on-chip distributed power supply systems. The measured transition time is less than 5ns with load circuit equivalent to 25k logic gates in 0.18-mum CMOS. This is to be compared with the case without the accelerator of the order of mus and thus the acceleration by two orders of magnitude is achieved. Automatic generation of the timings in a self-aligned manner is also discussed","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129615046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 75MHz MRAM with Pipe-Lined Self-Reference Read Scheme for Mobile/Robotics Memory System 一种用于移动/机器人存储系统的带管道自参考读取方案的75MHz MRAM
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251679
Tae Yun Kim, F. Kimura, Y. Matsui, T. Yoshihara, T. Ooishi, Y. Kihara, M. Hatanaka
{"title":"A 75MHz MRAM with Pipe-Lined Self-Reference Read Scheme for Mobile/Robotics Memory System","authors":"Tae Yun Kim, F. Kimura, Y. Matsui, T. Yoshihara, T. Ooishi, Y. Kihara, M. Hatanaka","doi":"10.1109/ASSCC.2005.251679","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251679","url":null,"abstract":"In this paper, we propose a pipe-lined self-reference read scheme of MRAM with read modify write which can make an operation period short. It also brings continuous read out accompanied with a mixed mat architecture. A new self-reference sense amplifier supported by a voltage transferred circuit has a wide margin. It is able to tolerate 50% MTJ resistance variation for sensing operation, and makes 75MHz operation at 1.2V Vcc possible. It brings a robust memory module for embedded memory system and suits mobile/robotics synchronous memory system","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129031801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis 用于精确静态时序分析的逻辑门输入电容建模
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251763
T. Kouno, M. Hashimoto, H. Onodera
{"title":"Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis","authors":"T. Kouno, M. Hashimoto, H. Onodera","doi":"10.1109/ASSCC.2005.251763","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251763","url":null,"abstract":"This paper discusses how to improve input capacitance modeling of logic gates for accurate STA (static timing analysis). The input capacitance of logic gates exhibits nonlinear behavior with respect to input signal voltage. Also, its value varies depending on the driving condition of stable inputs as well as loading of multiple-input gates condition of the gate. For the non-linearity issue, the authors propose to use an equivalent capacitance value derived by the integration of input current during partial transition instead of full transition. For the second issue, the authors suggest to consider the minimum capacitance as well as the maximum capacitance, which will eliminate possible errors in the shortest path calculation for hold violation analysis","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121199611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Large-Displacement CMOS-Micromachined Thermal Actuator with Capacitive Position Sensing 电容式位置传感的大位移cmos微机械热致动器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251814
Li Zheng, M.S.-C. Lu
{"title":"A Large-Displacement CMOS-Micromachined Thermal Actuator with Capacitive Position Sensing","authors":"Li Zheng, M.S.-C. Lu","doi":"10.1109/ASSCC.2005.251814","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251814","url":null,"abstract":"In this paper, we present the design and characterization of a large-displacement thermal actuator fabricated in a conventional CMOS process. The thermally-driven microstructure is fabricated by two dry etching steps after the completion of CMOS. The structure contains multiple layers of metal, silicon dioxide, and polysilicon. To avoid drift caused by change of ambient temperature, we adopt a capacitive sensing scheme that uses vertically sensed comb electrodes with a nominal sensing capacitance of 40 fF. The microactuator is characterized by static and dynamic measurements, with a measured out-of-plane motion up to 24 mum at 17 mW, a thermal time constant of 0.24 ms, and a mechanical resonant frequency at 16.8 kHz. The measured minimum input-referred noise voltage of the sensing preamplifier is 5.9 muV/radicHz, equivalent to a minimum input-referred noise displacement of 0.16 nm/radicHz","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 1.2Mpixels/s/mW 3-D Rendering Processor For Portable Multimedia Application 用于便携式多媒体应用的120万像素/秒/兆瓦3-D渲染处理器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251724
Jeong-Ho Woo, Min-wuk Lee, Hyejung Kim, Ju-Ho Sohn, H. Yoo
{"title":"A 1.2Mpixels/s/mW 3-D Rendering Processor For Portable Multimedia Application","authors":"Jeong-Ho Woo, Min-wuk Lee, Hyejung Kim, Ju-Ho Sohn, H. Yoo","doi":"10.1109/ASSCC.2005.251724","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251724","url":null,"abstract":"A 1.2Mpixles/s/mW 3D rendering processor is designed and implemented for portable multimedia application. A sustained 20Mpixels/s pixel fill rate is obtained at 10MHz with the help of embedded depth buffer and recursive sub-block mapped texture cache. In order to achieve low power rendering operation, SlimShader architecture with non-atomic read-modify-write scheme and logarithmic datapath is employed. The rendering processor consists of 281k logic gates and 164kB embedded SRAM in 25mm2. It is fabricated in 0.18mum 1-poly 6-metal CMOS logic process and real-time 3D graphics images are successfully demonstrated on the system evaluation board. It consumes 17mW at 10MHz while drawing texture-mapped 3D graphics images","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133671547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 1.1-Gb/s 4092-bit Low-Density Parity-Check Decoder 1.1 gb /s 4092位低密度奇偶校验解码器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251709
E. Yeo, B. Nikolić
{"title":"A 1.1-Gb/s 4092-bit Low-Density Parity-Check Decoder","authors":"E. Yeo, B. Nikolić","doi":"10.1109/ASSCC.2005.251709","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251709","url":null,"abstract":"A 4092-bit low-density parity-check decoder, based on staggered decoding schedule, is implemented in a 130nm 6M CMOS technology. The rate 0.75 code is based on finite-field geometries. Serial, shift-register based architecture enables a compact decoder implementation. The chip has a 4.0mm2 core and operates at 1.1 GHz with 1.2V supply, resulting in a throughput of 1.1Gb/s per iteration","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132676074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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