95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping

Abstract

Low-power FPGA architecture is proposed based on fine-grained V _DD control scheme called micro-V_DD-hopping. Four configurable logic blocks (CLB) are grouped into one block where V_DD is shared. In the micro-V_DD-hopping scheme, V _DD of each block is varied between the higher V_DD (V_DDH) and the lower V_DD (V_DDL) spatially and temporally to achieve lower power, while keeping performance undegraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. The proposed FPGA is fabricated using 035mum CMOS technology together with the conventional fixed-V_DD FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the highest speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGA is 2%