A Multimode GSM/DCS/WCDMA Double Loop Frequency Synthesizer

2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI:10.1109/ASSCC.2005.251700

Franck Badets, Laurent Camino, S. Dedieu, D. Belot, Sébastien Rieubon, Thiery Divel, Patrick Cerisier

引用次数: 12

Abstract

In this paper a WCDMA/GSM/DCS/PCS multimode frequency synthesizer is presented. It consists in a double loop synthesizer with a programmable divider between each integer synthesizer in order to provide fractional steps. The synthesizer has been implemented in a STMicroelectronics 0.25 mum RF BiCMOS technology. Measured phase noise at 400 kHz of the 3.8 GHz carrier is -118 dBc/Hz. Power consumption is about 21 mA from a 2.5 V battery

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多模GSM/DCS/WCDMA双回路频率合成器

本文介绍了一种WCDMA/GSM/DCS/PCS多模频率合成器。它由一个双回路合成器组成，每个整数合成器之间有一个可编程分配器，以便提供分数阶。该合成器采用意法半导体0.25 μ m射频BiCMOS技术。在3.8 GHz载波400 kHz处测量的相位噪声为-118 dBc/Hz。2.5 V电池的功耗约为21毫安

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2005 IEEE Asian Solid-State Circuits Conference

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