Jeong-Ho Woo, Min-wuk Lee, Hyejung Kim, Ju-Ho Sohn, H. Yoo
{"title":"A 1.2Mpixels/s/mW 3-D Rendering Processor For Portable Multimedia Application","authors":"Jeong-Ho Woo, Min-wuk Lee, Hyejung Kim, Ju-Ho Sohn, H. Yoo","doi":"10.1109/ASSCC.2005.251724","DOIUrl":null,"url":null,"abstract":"A 1.2Mpixles/s/mW 3D rendering processor is designed and implemented for portable multimedia application. A sustained 20Mpixels/s pixel fill rate is obtained at 10MHz with the help of embedded depth buffer and recursive sub-block mapped texture cache. In order to achieve low power rendering operation, SlimShader architecture with non-atomic read-modify-write scheme and logarithmic datapath is employed. The rendering processor consists of 281k logic gates and 164kB embedded SRAM in 25mm2. It is fabricated in 0.18mum 1-poly 6-metal CMOS logic process and real-time 3D graphics images are successfully demonstrated on the system evaluation board. It consumes 17mW at 10MHz while drawing texture-mapped 3D graphics images","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2005.251724","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A 1.2Mpixles/s/mW 3D rendering processor is designed and implemented for portable multimedia application. A sustained 20Mpixels/s pixel fill rate is obtained at 10MHz with the help of embedded depth buffer and recursive sub-block mapped texture cache. In order to achieve low power rendering operation, SlimShader architecture with non-atomic read-modify-write scheme and logarithmic datapath is employed. The rendering processor consists of 281k logic gates and 164kB embedded SRAM in 25mm2. It is fabricated in 0.18mum 1-poly 6-metal CMOS logic process and real-time 3D graphics images are successfully demonstrated on the system evaluation board. It consumes 17mW at 10MHz while drawing texture-mapped 3D graphics images
针对便携式多媒体应用,设计并实现了一个1.2Mpixles/s/mW的3D渲染处理器。利用嵌入式深度缓冲和递归子块映射纹理缓存,在10MHz下获得了持续的20Mpixels/s像素填充率。为了实现低功耗的渲染操作,采用了非原子读-修改-写模式和对数数据路径的SlimShader架构。渲染处理器由281k逻辑门和164kB嵌入式SRAM组成,面积为25mm2。该系统采用0.18 μ m 1聚6金属CMOS逻辑工艺制作,并在系统评估板上成功展示了实时三维图形图像。在绘制纹理映射的3D图形图像时,它在10MHz下消耗17mW