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2005 IEEE Asian Solid-State Circuits Conference最新文献

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A Comparison between 63nm 8Gb and 90nm 4Gb Multi-Level Cell NAND Flash Memory for Mass Storage Application 大容量存储应用中63nm 8Gb和90nm 4Gb多级Cell NAND闪存的比较
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251777
D. Byeon, Sungsoo Lee, Y. Lim, Dongku Kang, Wook-Kee Han, Dong-Hwan Kim, K. Suh
{"title":"A Comparison between 63nm 8Gb and 90nm 4Gb Multi-Level Cell NAND Flash Memory for Mass Storage Application","authors":"D. Byeon, Sungsoo Lee, Y. Lim, Dongku Kang, Wook-Kee Han, Dong-Hwan Kim, K. Suh","doi":"10.1109/ASSCC.2005.251777","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251777","url":null,"abstract":"This paper compares design concepts of 63nm-8Gb and 90nm-4Gb multilevel cell (MLC) NAND flash memory. For 8Gb MLC NAND flash memory, locations of peripheral circuits and charge pumps are determined to optimize area and signal speed. Page buffer is simplified by reducing the number of transistors with minimal connections thereby resulting in smaller size. Performance is improved by using fast-read/write cycle and reduced signal paths. Furthermore, two-MAT-cell-array architecture is used for 2times read/write operations. Various techniques are used to suppress noisy effects such as common source line (CSL) noise and floating-gate-coupling noise","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"491 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123562666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Ultra-Low-Voltage CMOS Static Frequency Divider 超低电压CMOS静态分频器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251702
Jun-Chau Chien, Liang-Hung Lu
{"title":"Ultra-Low-Voltage CMOS Static Frequency Divider","authors":"Jun-Chau Chien, Liang-Hung Lu","doi":"10.1109/ASSCC.2005.251702","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251702","url":null,"abstract":"This paper presents an ultra-low-voltage static frequency divider fabricated in a standard 0.18-mum CMOS technology. Employing forward body-biasing (FBB) technique and parallel current switching topology, the 2:1 frequency divider operates up to 4.5 GHz while consuming 2.7 mW from a supply voltage of 0.6 V. When operating at a supply voltage of 0.7 V, a maximum operating frequency of 6.6 GHz is achieved at the cost of higher power dissipation","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"3350 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127498901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A CMOS Gm-C Analog Pre-Equalizer for 1000BASE-T Analog Receive Filters 用于1000BASE-T模拟接收滤波器的CMOS Gm-C模拟预均衡器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251693
Jingyu Huang, R. Spencer
{"title":"A CMOS Gm-C Analog Pre-Equalizer for 1000BASE-T Analog Receive Filters","authors":"Jingyu Huang, R. Spencer","doi":"10.1109/ASSCC.2005.251693","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251693","url":null,"abstract":"This paper presents a CMOS implementation of an analog pre-equalizer used in 1000BASE-T analog front ends. The purpose of this filter is to simplify the overall receiver complexity by providing partial equalization before the analog-to-digital converter. The filter architecture is decided in conjunction with the design of 1000BASE-T receivers and the constraints of process and power supply. The proposed filter, which has one zero and two poles, is implemented by a Gm -C filter in a 0.25mum 1-poly 5-metal digital CMOS process. A new linearization circuit is used in the transconductance cells to meet the linearity requirement even with a low power-supply voltage. System-level simulations indicate that the filter can reduce the overall receiver power and area without sacrificing performance. Measurements show that the filter response can be programmed for cable lengths from 10m to 150m, the total harmonic distortion is -47.5dB with a 1VPP input at 13.4MHz, and the input dynamic range is 51dB. The total power dissipation is 25mW from a single 2.5V power supply, and the active area is 0.5mm2","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121334769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quadrature Oscillator with Negative-Resistance Compensated Transformer Couple 带负电阻补偿变压器偶的正交振荡器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251760
B. Chi, Xiaolei Zhu, Ziqiang Wang, Zhihua Wang
{"title":"Quadrature Oscillator with Negative-Resistance Compensated Transformer Couple","authors":"B. Chi, Xiaolei Zhu, Ziqiang Wang, Zhihua Wang","doi":"10.1109/ASSCC.2005.251760","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251760","url":null,"abstract":"A quadrature oscillator with the negative-resistance compensated transformer couple is presented. Two identical LC sub-harmonic oscillators are cross-coupled by the transformer to generate the quadrature outputs. The transformer also serves as the tail current source filtering network for the sub-harmonic oscillators to improve the phase noise performance. The loss of the transformer is partially compensated by the cross-coupled PMOS pair to overcome the possible undesired harmonic couple and to further improve the phase noise performance. The phase noise performance of the quadrature oscillator is 7dB better than the sub-harmonic oscillator itself by the simulation. The quadrature oscillator has been implemented in 0.25mum CMOS process and the measurements show the proposed oscillator could achieve a phase noise of -130dBc/Hz at 1MHz offset from 1.13GHz carrier while it only draws an 8.0mA current from the 2.5V power supply","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128564187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Audio-Specific Signal Processor(ASSP) for High-Quality Audio Codec 用于高质量音频编解码器的音频专用信号处理器(ASSP)
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251757
J. H. Ryu, S. H. Yoon, M. Sunwoo, J. Moon
{"title":"Audio-Specific Signal Processor(ASSP) for High-Quality Audio Codec","authors":"J. H. Ryu, S. H. Yoon, M. Sunwoo, J. Moon","doi":"10.1109/ASSCC.2005.251757","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251757","url":null,"abstract":"This paper proposes an audio-specific signal processor for a high-quality audio codec. Filter bank calculation and Huffman decoding require massive computation in MPEG-2/4 AAC decoding. Therefore, the proposed architecture is specially designed for these tasks. The proposed architecture has two optimized units for the IMDCT (inverse modified discrete cosine transform) and Huffman decoding. Performance comparisons show significant improvement compared with other commercial DSPs. The proposed ASSP has been synthesized using the Samsung SEC 0.18 mum standard cell library. The proposed ASSP core consists of 120,283 gates and runs at 200 MHz","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114589691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 865-μW H.264/AVC Video Decoder for Mobile Applications 一个865 μ w的移动应用H.264/AVC视频解码器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251725
Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, K. Hou, Jiun-Yan Yang, Chen-Yi Lee
{"title":"An 865-μW H.264/AVC Video Decoder for Mobile Applications","authors":"Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, K. Hou, Jiun-Yan Yang, Chen-Yi Lee","doi":"10.1109/ASSCC.2005.251725","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251725","url":null,"abstract":"A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865-muW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4times4 sub-block level pipelining that achieves better buffer allocation and decoding throughput. In addition, several modules are designed with new features to improve overall system throughput (up to 260,000 macro-block/sec). The proposed solution integrates 456-k logic gates with 161Kb of embedded SRAM in 0.18-mum single-poly six-metal CMOS process with area of 11.3mm2","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133312594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique 段加权随机BIST (SWR-BIST):一种低功耗的BIST技术
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251733
Chun-Yi Lee, C. Li
{"title":"Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique","authors":"Chun-Yi Lee, C. Li","doi":"10.1109/ASSCC.2005.251733","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251733","url":null,"abstract":"This paper presents a segment weighted random built-in self test (SWR-BIST) technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transitions are minimized. In addition, scan cells in segments of the same weight are reordered to further reduce the scan-out transitions. Experiments on ISCAS circuits show that, compared with the pseudo random BIST, SWR-BIST effectively reduces the test power by 74%. The SWR-BIST circuitry is very small and it grows slowly with the CUT size. The penalty of this technique is area and routing overhead for scan chain reordering","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130268417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1.3-2.8 GHz Wide Range CMOS LC-VCO Using Variable Inductor 采用可变电感的1.3-2.8 GHz宽量程CMOS LC-VCO
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251716
Yusaku Ito, Y. Yoshihara, H. Sugawara, Kenichi Okada, K. Masu
{"title":"A 1.3-2.8 GHz Wide Range CMOS LC-VCO Using Variable Inductor","authors":"Yusaku Ito, Y. Yoshihara, H. Sugawara, Kenichi Okada, K. Masu","doi":"10.1109/ASSCC.2005.251716","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251716","url":null,"abstract":"This paper proposes a novel wide-range tunable CMOS voltage controlled oscillator (VCO). VCO uses an on-chip variable inductor and switched capacitors as variable elements. The VCO was fabricated using a standard 0.18mum CMOS process with five metal layers. The oscillation frequency can be tuned from 1.28 GHz to 2.75 GHz with tuning range of 72%. The proposed VCO operates with low phase noise, and it achieves high FOMT -205.9 dBc/Hz","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116205841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A 2.5Gbps Burst-Mode Clock and Data Recovery Circuit 2.5Gbps突发模式时钟和数据恢复电路
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251764
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
{"title":"A 2.5Gbps Burst-Mode Clock and Data Recovery Circuit","authors":"Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu","doi":"10.1109/ASSCC.2005.251764","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251764","url":null,"abstract":"A 2.5Gbps burst-mode CDR circuit is fabricated in 0.18mum CMOS process. The data generator for this CDR circuit is presented with reduced hardware and low power dissipation. The tight timing budget of the clock generator is also relaxed. The bit error rate less than 10-12 is achieved for a PRBS of 231-1 with 500ppm frequency deviation. The area of the digital core is 0.36mm2 and the power of 33mW/port is achieved for a 1.8V supply","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114778686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2.4GHz CMOS Quadrature VCO for 2.4GHz WLAN/Bluetooth Applications 用于2.4GHz WLAN/蓝牙应用的2.4GHz CMOS正交VCO
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251785
Jung-Yu Chang, Chia-Hsin Wu, Shen-Iuan Liu
{"title":"A 2.4GHz CMOS Quadrature VCO for 2.4GHz WLAN/Bluetooth Applications","authors":"Jung-Yu Chang, Chia-Hsin Wu, Shen-Iuan Liu","doi":"10.1109/ASSCC.2005.251785","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251785","url":null,"abstract":"A 2.4GHz low-phase-noise and low-phase-error LC tank quadrature voltage controlled oscillator (QVCO) using the parasitic vertical BJT coupling and RC phase shifters is presented. Based on the proposed techniques, the proposed QVCO can simultaneously have low phase noise and low phase error. This QVCO circuit has been realized in a 0.18mum triple-well CMOS process and exhibits below 0.2deg phase error with phase noise of -105dBc/Hz at 100kHz offset frequency. The tuning range is 380MHz from 2.27GHz to 2.65GHz with control voltage from 0.3V to 1.8V. It consumes 5.4mW at each tank","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128241786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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