{"title":"Audio-Specific Signal Processor(ASSP) for High-Quality Audio Codec","authors":"J. H. Ryu, S. H. Yoon, M. Sunwoo, J. Moon","doi":"10.1109/ASSCC.2005.251757","DOIUrl":null,"url":null,"abstract":"This paper proposes an audio-specific signal processor for a high-quality audio codec. Filter bank calculation and Huffman decoding require massive computation in MPEG-2/4 AAC decoding. Therefore, the proposed architecture is specially designed for these tasks. The proposed architecture has two optimized units for the IMDCT (inverse modified discrete cosine transform) and Huffman decoding. Performance comparisons show significant improvement compared with other commercial DSPs. The proposed ASSP has been synthesized using the Samsung SEC 0.18 mum standard cell library. The proposed ASSP core consists of 120,283 gates and runs at 200 MHz","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2005.251757","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes an audio-specific signal processor for a high-quality audio codec. Filter bank calculation and Huffman decoding require massive computation in MPEG-2/4 AAC decoding. Therefore, the proposed architecture is specially designed for these tasks. The proposed architecture has two optimized units for the IMDCT (inverse modified discrete cosine transform) and Huffman decoding. Performance comparisons show significant improvement compared with other commercial DSPs. The proposed ASSP has been synthesized using the Samsung SEC 0.18 mum standard cell library. The proposed ASSP core consists of 120,283 gates and runs at 200 MHz