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2005 IEEE Asian Solid-State Circuits Conference最新文献

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A 90 dBΩ, 10 Gbps Optical Receiver in a 0.18 μm CMOS Technology 基于0.18 μm CMOS技术的90 dBΩ， 10gbps光接收器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251694
Wei-Zen Chen, D. Lin
{"title":"A 90 dBΩ, 10 Gbps Optical Receiver in a 0.18 μm CMOS Technology","authors":"Wei-Zen Chen, D. Lin","doi":"10.1109/ASSCC.2005.251694","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251694","url":null,"abstract":"A 90 dBOmega optical receiver analog front-end (AFE), including a transimpedance amplifier, an automatic gain control circuit, and a post amplifier, is fabricated using a 0.18 mum CMOS technology. The receiver front-end provides a -3 dB bandwidth of 7.86 GHz and a GBW of 248.5 THz-Omega that exceeds the state of the arts. The photo current received by the receiver AFE is amplified to a differential voltage swing of 900 mVpp when driving 50 Omega output loads. The sensitivity of the optical receiver is -13 dBm at a bit error rate of 10 - 12 with a 231-1 PRBS test pattern","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133244899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1.8-V 531-mW Single-Chip Single-Conversion CMOS Cable TV Tuner 一种1.8 v 531mw单芯片单转换CMOS有线电视调谐器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251787
R. Wang, S. Lou, D. Lau, E. Wang, G. Wong, H. Luong
{"title":"A 1.8-V 531-mW Single-Chip Single-Conversion CMOS Cable TV Tuner","authors":"R. Wang, S. Lou, D. Lau, E. Wang, G. Wong, H. Luong","doi":"10.1109/ASSCC.2005.251787","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251787","url":null,"abstract":"An integrated analog tuner for open-cable applications is designed in a standard 0.18-mum CMOS process using single-conversion architecture. The tuner integrates a whole signal path including a wide-band low-noise amplifier, a novel image-rejection mixer, and a fully-integrated integer-N frequency synthesizer with a wide-band ring VCO. At 1.8-V supply and over the whole input frequency range from 54 MHz to 880 MHz, the tuner measures image rejection of 63-dB, maximum noise figure of 8.5-dB, IIP2 of 80.9 dBmV and IIP3 of 55.8 dBmV corresponding to CTB of -53.8 dBc and CSO of -54.3 dBc. The tuner dissipates a total of 531 mW while occupying a chip area of 5.4 mm 2","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130566562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Global High-Speed Signaling in Nanometer CMOS 纳米CMOS中的全局高速信号
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251748
J. Jaeyoung Kang, J. Park, M. Flynn
{"title":"Global High-Speed Signaling in Nanometer CMOS","authors":"J. Jaeyoung Kang, J. Park, M. Flynn","doi":"10.1109/ASSCC.2005.251748","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251748","url":null,"abstract":"A practical transmission line scheme, for long-range (-10 mm) on-chip, digital signaling in a conventional digital CMOS process is presented. Unlike other schemes, there is no requirement for up-conversion, equalization, or special metal processing. The new scheme eliminates the dispersion associated with long lossy lines, allowing very high rates (>40 Gb/s) to be achieved. Eye diagrams, based on line characteristics derived from EM simulation, indicate minimal inter-symbol interference at 40 Gb/s. For a 40 Gb/s link, in 130 nm CMOS, power consumption is shown to be less than a quarter that of a conventional parallel bus with optimally placed repeaters. The performance of a 0.72 cm link implemented in standard digital 180 nm CMOS is verified with measurements","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116171821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An Experimental 1Mb 0.11um 4.5F2 1.8Volt Multilevel Vertical Split Gate Source Side Injection Test Vehicle for Giga-Bit Density NOR Flash Memory 实验性1Mb 0.11um 4.5F2 1.8伏多电平垂直分栅源侧注入试验车用于千兆比特密度NOR快闪存储器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251681
H. Tran, A. Ly, V. Sarin, S.T. Nguyen, H.Q. Nguyen, L. Hoang, Hyun Bai Kim, I. Nojima, D. Lee
{"title":"An Experimental 1Mb 0.11um 4.5F2 1.8Volt Multilevel Vertical Split Gate Source Side Injection Test Vehicle for Giga-Bit Density NOR Flash Memory","authors":"H. Tran, A. Ly, V. Sarin, S.T. Nguyen, H.Q. Nguyen, L. Hoang, Hyun Bai Kim, I. Nojima, D. Lee","doi":"10.1109/ASSCC.2005.251681","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251681","url":null,"abstract":"An experimental 0.11mum 4.5F2 1.8V multilevel 1Mb vertical floating gate split gate source side injection (SSI) test vehicle for Giga-bit NOR flash memory is shown for the first time. Novel coupled sense line programming for 25mV precise charge placement and novel low cell current ~10ua mode source follower sense amplifier is shown to enable high speed high density G-bit MLC NOR flash memory system","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121819225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Sub-1V CMOS 2.5Gb/s Serial Link Transceiver Using 2X Oversampling 采用2X过采样的Sub-1V CMOS 2.5Gb/s串行链路收发器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251801
Chih-Chien Hung, Ming-Cheng Chiang, A. Lee, Sheng-Chou Lee
{"title":"A Sub-1V CMOS 2.5Gb/s Serial Link Transceiver Using 2X Oversampling","authors":"Chih-Chien Hung, Ming-Cheng Chiang, A. Lee, Sheng-Chou Lee","doi":"10.1109/ASSCC.2005.251801","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251801","url":null,"abstract":"This paper presents the design of a 2.5Gb/s serial link transceiver with a power consumption of 70mW. With IV supply voltage, the transceiver achieves the bit error rate of 10-14. A supply regulated PLL is shared by the transmitter and the receiver to facilitate the low-power and low-voltage design. The output jitter of the transmitter is 53.9ps peak-to-peak and the chip area is approximately 0.54 mm2","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122287847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultra Low-Cost 3.2Gb/s Optical-Rate Reed Solomon Decoder IC Design 超低成本3.2Gb/s光速率里德-所罗门解码器IC设计
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251795
Huai-Yi Hsu, Jih-Chiang Yeo, A. Wu
{"title":"Ultra Low-Cost 3.2Gb/s Optical-Rate Reed Solomon Decoder IC Design","authors":"Huai-Yi Hsu, Jih-Chiang Yeo, A. Wu","doi":"10.1109/ASSCC.2005.251795","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251795","url":null,"abstract":"Reed-Solomon (RS) code is a widely used forward error correction (FEC) technology to improve the channel impairments in the fiber communication systems. The typical parallel FEC architecture requires huge hardware cost to achieve very-high-speed transmission data rate for the optical systems. This paper presents an ultra low-cost VLSI architecture of RS decoder by using a novel just-in-time folding modified Euclidean algorithm (JIT-FMEA). The JIT-FMEA VLSI architecture can greatly reduce the hardware complexity by about 50% from the fully expanded parallel architecture, while it can achieve very high throughput rate for the 10Gbase-LX4 optical communication system. The proposed RS decoder architecture has been designed and implemented by using 0.18mum CMOS standard cell technology at the supply voltage of 1.8 V. Our design only requires about 21K gates and can achieve the data throughput rate of 3.2Gbit/s at clock frequency of 400MHz","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130132394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1.25 to 5Gbps LVDS Transmitter with a Novel Multi-Phase Tree-Type Multiplexer 1.25至5Gbps LVDS发射机，采用新型多相树型复用器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251747
Hungwen Lu, C. Su
{"title":"A 1.25 to 5Gbps LVDS Transmitter with a Novel Multi-Phase Tree-Type Multiplexer","authors":"Hungwen Lu, C. Su","doi":"10.1109/ASSCC.2005.251747","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251747","url":null,"abstract":"A novel multi-phase tree type multiplexer is proposed. It has the speed of the tree type multiplexer while operates at the clock rate of the multi-phase type multiplexer. The transmitter is implemented in 0.18 digital CMOS technology. It operates at the rate of 1.25Gbps to 5Gbps. The jitter is measured at 61ps at 5Gbps. The transmitter occupies an area of 300mum times 300mum and consumes 69.6mW of power","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126290193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1V Dual-Band VCO Using an Integrated Variable Inductor 采用集成可变电感的1V双频压控振荡器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251718
L. Leung, Kay W. C. Chui, H. Luong
{"title":"A 1V Dual-Band VCO Using an Integrated Variable Inductor","authors":"L. Leung, Kay W. C. Chui, H. Luong","doi":"10.1109/ASSCC.2005.251718","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251718","url":null,"abstract":"An integrated variable inductor is proposed using an on-chip transformer to obtain 2 inherent resonant modes for band-switching applications. Employing such a variable inductor in a 0.18-mum CMOS process at a 1-V supply, a VCO is demonstrated to oscillate in 2 distinct frequency bands from 2.2 GHz to 3.6 GHz and from 10.7 GHz to 11.3 GHz. The VCO measures phase noise of around -135.5 dBc/Hz for the lower band and around -126.5dBc/Hz for the upper band at 10-MHz offset while consuming 5mW and occupying an area of 0.4times0.8 mm2","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115520377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An Internal Voltage Generation System of Flash Memory Module Embedded in a Microcontroller 微控制器内嵌快闪记忆体内部电压产生系统
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251680
H. Tanikawa, T. Tanaka, A. Kato, T. Yamaki, Y. Umemoto, J. Ishikawa, T. Shimozato, I. Nakamura, Y. Shinagawa
{"title":"An Internal Voltage Generation System of Flash Memory Module Embedded in a Microcontroller","authors":"H. Tanikawa, T. Tanaka, A. Kato, T. Yamaki, Y. Umemoto, J. Ishikawa, T. Shimozato, I. Nakamura, Y. Shinagawa","doi":"10.1109/ASSCC.2005.251680","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251680","url":null,"abstract":"We present a new internal voltage generation system of flash memory module embedded in a microcontroller. One of the features is wide range voltage generator for the evaluation of the memory cell, which is effective mainly at the development early stage. The second feature is new temperature dependency voltage generator matched to memory cell property for the improvement of reliability. The third is an auto-trimming system that arranges output of internal voltage generators with target values. Using embedded CPU the auto-trimming system suppresses voltage variations for many chips simultaneously, so we can reduce test cost and improve reliability of flash memory module in the stage of mass production","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130901219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 5Gbps CMOS Automatic Gain Control Amplifier for 10GBase-LX 用于10GBase-LX的5Gbps CMOS自动增益控制放大器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251692
I-Hsin Wang, Wei-Sheng Chen, Shen-Iuan Liu
{"title":"A 5Gbps CMOS Automatic Gain Control Amplifier for 10GBase-LX","authors":"I-Hsin Wang, Wei-Sheng Chen, Shen-Iuan Liu","doi":"10.1109/ASSCC.2005.251692","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251692","url":null,"abstract":"A 5Gbps automatic gain control amplifier is presented with 27.8dB input dynamic range for 10GBase-LX4 Ethernet in 0.18mum CMOS technology. Five push-pull inverters use self-bias resistors and inductive-series peaking technique to realize a variable gain amplifier (VGA). This VGA achieves 4GHz bandwidth and 20dB linear-in-dB gain tuning range. The proposed 5Gbps AGC amplifier yields constant output amplitude 100mV for an input 27.8dB dynamic range","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130985956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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