Global High-Speed Signaling in Nanometer CMOS

Abstract

A practical transmission line scheme, for long-range (-10 mm) on-chip, digital signaling in a conventional digital CMOS process is presented. Unlike other schemes, there is no requirement for up-conversion, equalization, or special metal processing. The new scheme eliminates the dispersion associated with long lossy lines, allowing very high rates (>40 Gb/s) to be achieved. Eye diagrams, based on line characteristics derived from EM simulation, indicate minimal inter-symbol interference at 40 Gb/s. For a 40 Gb/s link, in 130 nm CMOS, power consumption is shown to be less than a quarter that of a conventional parallel bus with optimally placed repeaters. The performance of a 0.72 cm link implemented in standard digital 180 nm CMOS is verified with measurements