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2005 IEEE Asian Solid-State Circuits Conference最新文献

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A 10-GHz CMOS PLL with an Agile VCO Calibration 带有敏捷压控振荡器校准的10ghz CMOS锁相环
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251703
Yu-Jen Lai, Tsung-Hsien Lin
{"title":"A 10-GHz CMOS PLL with an Agile VCO Calibration","authors":"Yu-Jen Lai, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2005.251703","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251703","url":null,"abstract":"This paper reports a fully-integrated 10-GHz CMOS PLL with an agile VCO frequency calibration circuit. The proposed method automatically searches for the optimum VCO tuning curve out of a band of curves using much less time than other existing approaches. The agility is due to the novel searching technique which is based on the comparison of signal periods, rather than counting signal cycles or reading the VCO control voltage after the PLL settled. The proposed PLL is implemented in a 0.18-mum CMOS process. The measured PLL output phase noise at 10 GHz is -102 dBc/Hz at 1-MHz offset frequency and the reference spurs are below -48 dBc. The PLL consumes 44 mW in the low-current mode. The calibration time is less than 4 musec","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128484384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Fast-Switching Frequency Synthesizer for UWB Applications 一种用于超宽带应用的快速开关频率合成器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251699
Che-Fu Liang, Shen-Iuan Liu
{"title":"A Fast-Switching Frequency Synthesizer for UWB Applications","authors":"Che-Fu Liang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2005.251699","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251699","url":null,"abstract":"A fast-switching frequency synthesizer is presented for ultra-wideband MB-OFDM applications. This synthesizer generates three frequency tones with 528 MHz spacing. By using single-sideband mixers with Q-enhancement bandpass filters and switched-cascode multiplexers, the sideband rejection is less than -30dB at least and the frequency switching time is less than 7ns. The chip has been fabricated in 0.18mum CMOS process and the area is 1.32mm2. It consumed 70mW from a 1.8V supply","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"517 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127049729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On-demand Pipelining for Improving Energy-Awareness 提高能源意识的按需流水线
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251769
Chin‐Hung Liu, Tay-Jyi Lin, Chie-Wei Liu, C. Jen
{"title":"On-demand Pipelining for Improving Energy-Awareness","authors":"Chin‐Hung Liu, Tay-Jyi Lin, Chie-Wei Liu, C. Jen","doi":"10.1109/ASSCC.2005.251769","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251769","url":null,"abstract":"Clock gating is a well-known technique to reduce the clock pulses when a pipelined data path does not reach its peak throughput. This paper presents an on-demand pipelining scheme to further eliminate all redundant clock transitions, where the synchronization elements (i.e. registers or latches) are activated only when necessary. In our experiments with the UMC 0.18mum CMOS technology, the proposed approach saves up to 61% energy dissipation on conventional pipelines and 13% of those with gating clocks only. In contrast with the constant energy dissipation of the conventional clock gating approach, our on-demand pipelining consumes less and less energy as the allowed computation cycles increase for a given task. In other words, the proposed scheme has better energy awareness over varying throughput requirements","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121561111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA Prototype for WLAN OFDM Baseband with STPE of I/Q Mismatch Self Calibration Algorithm 基于I/Q失配自校正算法的WLAN OFDM基带FPGA原型
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251789
Chia-Hung Hsu, Chih-Feng Wu, Chorng-Kuang Wang
{"title":"FPGA Prototype for WLAN OFDM Baseband with STPE of I/Q Mismatch Self Calibration Algorithm","authors":"Chia-Hung Hsu, Chih-Feng Wu, Chorng-Kuang Wang","doi":"10.1109/ASSCC.2005.251789","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251789","url":null,"abstract":"Based on the single tone power evaluation (STPE), a self-calibration algorithm of I/Q mismatch is proposed for the IEEE 802.11a WLAN systems. The self-calibration algorithm is performed by the digital baseband at transceiver start-up to measure the signal power of the single tone signal, which is located at the double frequency band at the receiver. Furthermore, the residual I/Q mismatch is tracked during the physical data transmission. Therefore, the design requirements of the RF front-end for the WLAN OFDM transceiver are alleviated. According to the proposed algorithm, the residual signal-to-noise ratio (SNR) degradation is totally less than 0.5-dB with plusmn5% gain mismatch (DeltaG) and plusmn5deg phase mismatch (Deltathetas) in the transmitter and receiver respectively, and carrier frequency offset (CFO = plusmn232kHz). Finally, the prototype of the IEEE 802.11a WLAN baseband is realized by the Altera Stratix EP1S80 DSP development board with about 32000 logic elements at 40MHz","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121619692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
4 Gbps On-Chip Interconnection using Differential Transmission Line 采用差分传输线的4gbps片上互连
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251754
H. Ito, H. Sugita, K. Okada, K. Masu
{"title":"4 Gbps On-Chip Interconnection using Differential Transmission Line","authors":"H. Ito, H. Sugita, K. Okada, K. Masu","doi":"10.1109/ASSCC.2005.251754","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251754","url":null,"abstract":"This paper demonstrates the differential transmission line interconnect for high-speed global interconnect IP. The interconnect is fabricated using a 180 nm CMOS technology. 4 Gbps signal transmission can be achieved in measurement results. The on-chip transmission line performs faster signal transmission than common RC interconnects","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124257158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A Wireless-Interface SoC Powered by Energy Harvesting for Short-range Data Communication 一种用于短距离数据通信的能量收集供电的无线接口SoC
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251710
S. Mikami, T. Matsuno, M. Miyama, M. Yoshimoto, H. Ono
{"title":"A Wireless-Interface SoC Powered by Energy Harvesting for Short-range Data Communication","authors":"S. Mikami, T. Matsuno, M. Miyama, M. Yoshimoto, H. Ono","doi":"10.1109/ASSCC.2005.251710","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251710","url":null,"abstract":"This paper describes the design and estimation of a wireless-interface SoC for wireless battery-less mouse with short-range data communication capability. It comprises an RF transmitter and microcontroller. An SoC, which is powered by an electric generator that exploits gyration energy by dragging the mouse, was fabricated using the TSMC 0.18-mum CMOS process. Features of the SoC are the adoption of a simple FSK modulation scheme, a single-end configuration on the RF transmitter, and the specific microcontroller design for mouse operation. We verified that the RF transmitter can perform data communication with a 1-m range at 2.17 mW, and the microcontroller consumes 0.03 mW at 1 MHz, which shows that the total power consumption in the SoC is 2.2 mW. This is sufficiently low for the SoC to operate with energy harvesting","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121540830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A High Efficiency ALL-PMOS Charge Pump for Low-Voltage Operations 一种用于低压操作的高效全pmos电荷泵
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251740
N. Yan, Hao Min
{"title":"A High Efficiency ALL-PMOS Charge Pump for Low-Voltage Operations","authors":"N. Yan, Hao Min","doi":"10.1109/ASSCC.2005.251740","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251740","url":null,"abstract":"This paper presents a high performance ALL-PMOS charge pump suitable for implementation in standard CMOS processes. And only low voltage PMOS transistors are used. With the switching substrate technique and boosted transistor, the influence of body effect is eliminated and output voltage is greatly increased. A twelve-stage charge pump circuit is fabricated in a 0.35-mum double-poly CMOS technology. Measurements at 3MHz have shown that for power supply voltages of 2 V, 1.5V and 1V an output voltage of 15.5V, 10.4V and 3.6V can be generated respectively","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121798808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A Fully Integrated CMOS RF Power Amplifier with Parallel Power Combining and Power Control 具有并联功率组合和功率控制的全集成CMOS射频功率放大器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251684
P. Reynaert, M. Steyaert
{"title":"A Fully Integrated CMOS RF Power Amplifier with Parallel Power Combining and Power Control","authors":"P. Reynaert, M. Steyaert","doi":"10.1109/ASSCC.2005.251684","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251684","url":null,"abstract":"This paper presents a fully integrated RF power amplifier (PA) operating at 2.45 GHz and integrated in a 0.13mum CMOS technology. To achieve an output power of 23dBm, the architecture consists of four amplifiers whose outputs are combined by an on-chip power combining and matching network. The power added efficiency is 28% at 2.45 GHz and -6dBm input power. At lower power levels, the efficiency is increased by using only one power amplifier. This technique reduces the power consumption of the driver stages. The presented fully integrated solution reduces the required board area and increases the overall transmitter efficiency","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127554582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Wide Band CDR for Digital Video Data Transmission 用于数字视频数据传输的宽带话单
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251782
S. Ozawa, S. Miura, S. Kousokabe, Y. Ishizone, S. Tomosugi, J. Okamura
{"title":"A Wide Band CDR for Digital Video Data Transmission","authors":"S. Ozawa, S. Miura, S. Kousokabe, Y. Ishizone, S. Tomosugi, J. Okamura","doi":"10.1109/ASSCC.2005.251782","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251782","url":null,"abstract":"This paper describes a wide band CDR with a new encoding scheme for a digital video data transmission. The CDR works from 105Mbps to 1365Mbps without any external frequency references. The proposed encoding scheme uses both PECT (periodic embedded clock transition) and PECT (periodic embedded clock period) scheme, and it helps the CDR's capture process. The CDR is using both digital and analog techniques. Digital block adjusts VCO frequency utilizing PECT and PECP scheme, and analog block maintains lock with small jitter. The device is fabricated on 0.35mum standard logic CMOS process","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116572593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Fast-Recovery Low Dropout Linear Regulator for Any-Type Output Capacitors 一种适用于任意类型输出电容的快速恢复低差线性稳压器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251786
Sao-Hung Lu, Wei-Jen Huang, Shen-Iuan Liu
{"title":"A Fast-Recovery Low Dropout Linear Regulator for Any-Type Output Capacitors","authors":"Sao-Hung Lu, Wei-Jen Huang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2005.251786","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251786","url":null,"abstract":"A 1.8-V, 150-mA fast settling low dropout linear regulator (LDO) with single Miller compensation capacitor is presented. By utilizing the digital-controlled dynamic bias circuit to track the output current, the proposed LDO provides fast settling time for the output capacitors with low and high equivalent series resistance (ESR). The proposed LDO has been fabricated in a 0.35-mum 2P4M CMOS technology, and the active chip area is 480mum times 675mum. The measurement results show the settling time of 4mus can be achieved with 0.5% error for full load-current changes for both multilayer ceramic and electrolytic 1-muF output capacitors. Furthermore, the line and load regulations are 0.127%N and 40ppm/mA, respectively. The dropout voltage is 190mV in 150mA output current. The measured quiescent current is 45muA in 5V supply voltage without output current","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127488548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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