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Low-Phase Noise LC-tank Quadrature Voltage Controlled Oscillator 低相位噪声LC-tank正交压控振荡器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251717
Chan-Young Jeong, Mi-Young Lee, C. Yoo
{"title":"Low-Phase Noise LC-tank Quadrature Voltage Controlled Oscillator","authors":"Chan-Young Jeong, Mi-Young Lee, C. Yoo","doi":"10.1109/ASSCC.2005.251717","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251717","url":null,"abstract":"A low phase noise LC-tank quadrature voltage controlled oscillator (QVCO) is described. Two differential pairs (one for negative gm generation and the other one for the coupling input) of each resonator have separate bias current sources which are switched on and off by the coupling input of each resonator. The measured results of 5GHz quadrature VCOs (QVCO) implemented in a 0.13mum CMOS process shows the proposed biasing scheme can improve the phase noise by 17dB from the conventional QVCO with constant tail current sources while the two QVCOs consume the same power (4.4mA from a 1.2V supply). The smaller 1/f noise of the switched current source improves the phase noise by 7dB. The additional 10 dB improvement of the phase noise is obtained by employing the coupling input as the switching signal and separating the tail current sources for the two differential pairs of each resonator","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128250483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A CMOS vision sensor with on-the-fly histogram equalization using TFS encoding and AER read-out 采用TFS编码和AER读出的动态直方图均衡的CMOS视觉传感器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251758
Shoushun Chen, A. Bermak, D. Martinez
{"title":"A CMOS vision sensor with on-the-fly histogram equalization using TFS encoding and AER read-out","authors":"Shoushun Chen, A. Bermak, D. Martinez","doi":"10.1109/ASSCC.2005.251758","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251758","url":null,"abstract":"This paper presents a CMOS vision sensor performing image capture and on-chip histogram equalization. Both image capture and the processing are based on time-to-first spike encoding combined with address event representation (AER) read-out scheme. The proposed approach not only provides a compact and efficient VLSI implementation but also eliminates voltage/current domain analog processing and hence provides immunity to dynamic range reduction caused by low voltage operation in advanced sub-micron technologies. The pixel values are read-out using an asynchronous handshaking type of read-out while the processing is carried out using simple and yet robust digital timer occupying a very small silicon area (0.1 times 0.6mm2 in 0.35mum CMOS). Low power operation (10nA per pixel) is achieved since the pixels are only allowed to switch once per frame and only active pixels are allowed to asynchronously access the bus. The prototype was implemented in 0.35mum CMOS technology with a silicon area of 3.1 times 3.2mm2","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130686050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low Power 0.18 μm CMOS Dual-Band Front-End 低功耗0.18 μm CMOS双带前端
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251812
K. Phansathitwong, H. Sjoland
{"title":"Low Power 0.18 μm CMOS Dual-Band Front-End","authors":"K. Phansathitwong, H. Sjoland","doi":"10.1109/ASSCC.2005.251812","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251812","url":null,"abstract":"A dual-band CMOS front-end was designed and fabricated in a 0.18 mum CMOS process. The front-end employs a common-gate low noise amplifier (LNA) with capacitive cross coupling (CCC) technique and a passive mixer. The band selection is performed by switching a capacitor in and out of the LNA load, changing the resonance frequency between 2.2GHz and 4.0GHz. The measured noise figure is below 3.5dB for both frequency bands for supply voltages from 1.8V down to 1V. The conversion gain is more than 10dB, and the third order intercept point (IIPs) is above -6dBm. The circuit draws 2.4mA from a 1V supply","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134143105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 3-mW, 270-Mbps, Clock-Edge Modulated Serial Link for Mobile Displays 用于移动显示器的3mw, 270-Mbps时钟边缘调制串行链路
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251803
Won-Jun Choe, Bong-Joon Lee, Jaeha Kim, D. Jeong, Gyudong Kim
{"title":"A 3-mW, 270-Mbps, Clock-Edge Modulated Serial Link for Mobile Displays","authors":"Won-Jun Choe, Bong-Joon Lee, Jaeha Kim, D. Jeong, Gyudong Kim","doi":"10.1109/ASSCC.2005.251803","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251803","url":null,"abstract":"In this paper, a single channel clock-edge modulated serial link for mobile display interface is presented. Clock edge modulation (CEM) enables all necessary signals between a graphic processor and a LCD timing controller to be transferred over a single, DC-balanced differential channel, thus greatly saving the power and costs of the existing parallel lines. A simple DLL-based CEM decoder is described that recovers the data with low power consumption and high jitter tolerance. The use of a voltage-mode driver and a single-side termination further reduces the power. A prototype CEM transceiver was implemented in a 0.18mum CMOS process and dissipates 3.12mW when operating at 270-Mb/s and 1.2V","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134149307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Single Polysilicon Gate High-Density Logic Using Independently-Controlled Double-Gate Devices 采用独立控制双栅器件的单多晶硅栅极高密度逻辑
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251738
M. Chiang, Keunwoo Kim, C. Chuang, C. Tretz
{"title":"Single Polysilicon Gate High-Density Logic Using Independently-Controlled Double-Gate Devices","authors":"M. Chiang, Keunwoo Kim, C. Chuang, C. Tretz","doi":"10.1109/ASSCC.2005.251738","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251738","url":null,"abstract":"Novel double-gate (DG) CMOS logic with a single polysilicon gate process is proposed using independently biased gates. The unique gate-to-gate coupling of DG devices is exploited to improve circuit density, capacitance, performance, and power in 25 nm logic circuits by halving the number of stacked transistors as well as parallel transistors for implementing logic functions. The performance, power, and design trade-offs as well as layouts for logic gates are analyzed via mixed-mode two-dimensional numerical simulations","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Power 60 dB Gain Range with 0.25 dB Resolution CMOS RF Programmable Gain Amplifier for Dual-band DAB/T-DMB Tuner IC 低功耗60 dB增益范围，0.25 dB分辨率CMOS射频可编程增益放大器，用于双频DAB/T-DMB调谐器IC
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251683
Tae Wook Kim, Bonkee Kim, Youngho Cho, Seyeob Kim, Boeun Kim, Kwyro Lee
{"title":"Low Power 60 dB Gain Range with 0.25 dB Resolution CMOS RF Programmable Gain Amplifier for Dual-band DAB/T-DMB Tuner IC","authors":"Tae Wook Kim, Bonkee Kim, Youngho Cho, Seyeob Kim, Boeun Kim, Kwyro Lee","doi":"10.1109/ASSCC.2005.251683","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251683","url":null,"abstract":"Low power CMOS RF digitally programmable gain amplifiers for dual-band (Band-III and L-Band) DAB/T-DMB receiver IC are implemented using 0.18 mum CMOS process. For a stable operation among large interference situation, it is required to have wide gain range and fine resolution in RF domain. In order to meet such requirements, various programmable gain amplifier architectures are proposed. Also employing a differential multiple gated transistor (DMGTR) technique which is a differential circuit gm\" cancellation method, maximum 22 dB IIP3 improvement is obtained. The IC exhibits 60 dB gain range with 0.25 dB resolution, 2.7 dB NF, -14 dBm IIP3 and 42 dB voltage gain at 22 mW power consumption for L-Band case, 50 dB gain range with 0.25 dB resolution, 3 dB NF, -5 dBm IIP3 and 28 dB voltage gain for Band-III case at 16mW power consumption","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131127671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Novel Test Structure to emulate Capacitance Variations of a Rate-Grade MEMS Gyroscope 一种模拟速率级MEMS陀螺仪电容变化的新型测试结构
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251753
R. Sangati, S. Syamala, N. Bhat
{"title":"Novel Test Structure to emulate Capacitance Variations of a Rate-Grade MEMS Gyroscope","authors":"R. Sangati, S. Syamala, N. Bhat","doi":"10.1109/ASSCC.2005.251753","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251753","url":null,"abstract":"In this paper a novel test structure, which emulates the capacitance variation of a MEMS gyroscope is presented. The rotational rate of the gyroscope is taken as an electrical signal which is converted into capacitance variations, that can be sensed by the sensor electronics. The continuous angular variations are converted into sampled capacitance changes proportional to the rotational rate. This obviates the need for multi-domain simulations and subsequently the multiple domain testing to validate the design of sensor electronics of the gyroscope. This helps in reducing the time to market and long product development cycles. The test structures are prototyped using 1.5mum technology and are validated using a novel charge/discharge technique which measures a minimum capacitance change of 5fF","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117173655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low Power 128Mb Pseudo SRAM Using Hyper Destructive Read Architecture 一种采用超破坏性读取架构的低功耗128Mb伪SRAM
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251678
Jin-Hong Ahn, Sang-Hoon Hong, Jae-Bum Ko, Se Jun Kim, Sung-Won Shin, Hee-Bok Kang, Jae-Jin Lee, J. Kih
{"title":"A Low Power 128Mb Pseudo SRAM Using Hyper Destructive Read Architecture","authors":"Jin-Hong Ahn, Sang-Hoon Hong, Jae-Bum Ko, Se Jun Kim, Sung-Won Shin, Hee-Bok Kang, Jae-Jin Lee, J. Kih","doi":"10.1109/ASSCC.2005.251678","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251678","url":null,"abstract":"A 128Mb pseudo SRAM is developed using a special type of architecture with the purpose of effectively reducing the standby current. Standby current, especially the off leakage current is becoming more difficult problem to handle in modern devices because shorter channel length in high density and high speed devices are at a point where off leakage is the major source. In order to solve this issue, hyper destructive read architecture (HyDRA) is developed. HyDRA is a special DRAM architecture enabling destructive reading of DRAM cells using global bitline and extra tag memory. The paper demonstrates HyDRA utilizing its fast row cycle capability to instead minimize standby power to 150muA @ 2.1V and 90degC while maintaining the speed and chip area of the conventional scheme using the same process technology","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122244508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3.3/5V Multi-rate Laser Diode Driver and Limiting Amplifier for Optical Transceivers 用于光收发器的3.3/5V多速率激光二极管驱动器和限制放大器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251802
Yu-Tung Chen, Chi-Luen Wang
{"title":"3.3/5V Multi-rate Laser Diode Driver and Limiting Amplifier for Optical Transceivers","authors":"Yu-Tung Chen, Chi-Luen Wang","doi":"10.1109/ASSCC.2005.251802","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251802","url":null,"abstract":"A laser diode driver and a limiting amplifier for multirate and multistandard optical transceiver modules from 155Mb/s to 2.1Gb/s had been developed using a 0.5-mum SiGe BiCMOS technology. With new driving circuit, the laser can be DC-coupled to the laser diode driver for reduced component count and ease of multi-rate operation. Automatic power control (APC), modulation compensation and built-in temperature-compensation are also achieved. Careful circuit design enables the limiting amplifier to realize better input sensitivity of 2mVp-p and provides approximately 50dB of gain. A novel received signal strength indicator (RSSI) circuit is proposed to accomplish the input signal-detect function, and the circuit complexity and current consumption can be reduced. A low-frequency feedback loop is integrated in the limiting amplifier to reduce input offset, making it below 100muV typically","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123949022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reconstructive Oscillator Based Sinusoidal Signal Generator for ADC BIST 基于重构振荡器的ADC BIST正弦信号发生器
2005 IEEE Asian Solid-State Circuits Conference Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251808
Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang
{"title":"Reconstructive Oscillator Based Sinusoidal Signal Generator for ADC BIST","authors":"Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang","doi":"10.1109/ASSCC.2005.251808","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251808","url":null,"abstract":"This paper presents a reconstructive oscillator based sinusoidal signal generator which can produce both high and low frequency signals by switching the oscillator into different mode. In addition, analog and digital signals can be produced concurrently in both modes. Also, signal amplitude and oscillation frequency can be precisely controlled compared with pure analog signal generator. Except for a 1-bit D/A converter and analog filter, the circuits are entirely constructed by digital circuits. One can trade the digital hardware complexity to moderate the difficulties in designing the analog reconstructive filter. The generated high and low frequency signals are suitable to serve as the test stimuli in built-in self test methodology for A/D converters to extract the transmission and static parameters, respectively","PeriodicalId":341932,"journal":{"name":"2005 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115797464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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