Practical Synthesis of 13-bit 40-MSample/s Pipelined ADC

Abstract

A 13-bit pipelined ADC achieving 67 dB SNDR without digital calibration while consuming 313mW @ 3.3V 40 MSPS is designed using analog synthesis tools. The MDACs in the pipeline have identical topology and can be synthesized to optimize pipeline performance in less than I day. Figure of merit of the three test keys comparing a manually designed, partially synthesized, and fully synthesized ADC is reported showing the efficacy and efficiency of the proposed approach