发布求助
文献互助 智能选刊 最新文献

2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)最新文献

筛选
英文 中文
A comprehensive ESD verification flow at transistor level for large SoC designs 一个全面的ESD验证流程在晶体管级的大型SoC设计
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314740
J. Lescot, Patrice Dehan, Wahbi Boujarra, D. Medhat, Sophie Billy
{"title":"A comprehensive ESD verification flow at transistor level for large SoC designs","authors":"J. Lescot, Patrice Dehan, Wahbi Boujarra, D. Medhat, Sophie Billy","doi":"10.1109/EOSESD.2015.7314740","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314740","url":null,"abstract":"A fast yet robust multi-domain ESD verification flow at transistor level has been developed for large SoC designs. All steps of the verification process from initial power domains configuration to the final debugging process are covered in this comprehensive solution that supports scalable ESD protection structures.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121204738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A novel new concept in hybrid alpha ionization systems 杂化电离系统的新概念
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314737
L. Levit, Geoffrey Weil
{"title":"A novel new concept in hybrid alpha ionization systems","authors":"L. Levit, Geoffrey Weil","doi":"10.1109/EOSESD.2015.7314737","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314737","url":null,"abstract":"A novel ionizer invention based upon a hybrid alpha and pulsed high voltage bias ionizer is presented. It Places the ionizer in the process chamber and biases it remotely through a plastic window using only fields. It performs very nearly identically to such an ionizer with hard wiring to the source. Because the circuit is a capacitor, the ionizer is automatically balanced so there is no need to adjust the balance.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122666323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Soft fails due to LU stress of virtual power domains 虚拟电源域的LU应力导致软故障
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314795
K. Domanski, H. Gossner
{"title":"Soft fails due to LU stress of virtual power domains","authors":"K. Domanski, H. Gossner","doi":"10.1109/EOSESD.2015.7314795","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314795","url":null,"abstract":"A shut-down of IC was caused by current injection into a USB 2.0 pin. Root cause was a substrate current forced into a power rail supplied by a weak LDO. Connecting the guard rings to a robust VDD supply resolved the problem. As the failure could not be revealed by JESD78 testing, a modified latchup test setup is proposed.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126330871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
3D integration ESD protection design and analysis 三维集成ESD防护设计与分析
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314791
S. Mitra, E. Gebreselasie, You Li, R. Gauthier, J. Silberman, C. Tyberg, K. Sakuma, T. Tran-Quinn, K. Ramachandran, M. Angyal
{"title":"3D integration ESD protection design and analysis","authors":"S. Mitra, E. Gebreselasie, You Li, R. Gauthier, J. Silberman, C. Tyberg, K. Sakuma, T. Tran-Quinn, K. Ramachandran, M. Angyal","doi":"10.1109/EOSESD.2015.7314791","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314791","url":null,"abstract":"A Design of Experiments (DOEs) matrix was created to evaluate probability of fails during a complex 3D integration process as a function of ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Based on measured samples, functionality test and leakage test show circuit performance degradation and larger fail rate after chip bonding on designs without ESD protection.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115966659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A passive coupling circuit for injecting TLP-like stress pulses into only one end of a driver/receiver system 一种被动耦合电路，用于将张力腿式应力脉冲注入驱动器/接收器系统的一端
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314800
Benjamin J. Orr, D. Johnsson, K. Domanski, H. Gossner, D. Pommerenke
{"title":"A passive coupling circuit for injecting TLP-like stress pulses into only one end of a driver/receiver system","authors":"Benjamin J. Orr, D. Johnsson, K. Domanski, H. Gossner, D. Pommerenke","doi":"10.1109/EOSESD.2015.7314800","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314800","url":null,"abstract":"In this paper, a simple passive circuit is presented which allows TLP stress and characterization pulses to be injected into only one side of a driver/receiver system. The circuit is simulated and tested, demonstrating the possibility for directional current injection on the order of 60:1. The circuit also provides a method for measuring both injected currents when paired with a typical TLP system.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124349138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new full-chip verification methodology to prevent CDM oxide failures 一种新的全芯片验证方法，防止CDM氧化物失效
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314811
M. Etherton, Scott Ruth, James W. Miller, Rishabh Agarwal, Rishi Bhooshan, M. Ershov, M. Cadjan, Y. Feinberg, K. Srinivasan, N. Chang, Youlin Liao
{"title":"A new full-chip verification methodology to prevent CDM oxide failures","authors":"M. Etherton, Scott Ruth, James W. Miller, Rishabh Agarwal, Rishi Bhooshan, M. Ershov, M. Cadjan, Y. Feinberg, K. Srinivasan, N. Chang, Youlin Liao","doi":"10.1109/EOSESD.2015.7314811","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314811","url":null,"abstract":"This paper describes a new full-chip CDM ESD verification method that enables the evaluation of complete integrated circuits (ICs) for CDM risk. We demonstrate that a robust analysis must comprehend millions of locations of driver-receiver (D/R) pairs on an IC, an accurate model of the grid resistance and an adequate representation of the CDM current distribution.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124538182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Multi-physics simulations for triboelectric charging of display panels during the roller transfer process 滚轮传递过程中显示面板摩擦电荷的多物理场模拟
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314744
Ki-hyuk Kim, D. Pommerenke, Y. Gan, Nam-Hee Goo, SeukWhan Lee
{"title":"Multi-physics simulations for triboelectric charging of display panels during the roller transfer process","authors":"Ki-hyuk Kim, D. Pommerenke, Y. Gan, Nam-Hee Goo, SeukWhan Lee","doi":"10.1109/EOSESD.2015.7314744","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314744","url":null,"abstract":"A multi-physics simulation methodology for triboelectric charging during the roller transfer process of display panels is proposed. Electrical and mechanical models for triboelectric charging are developed. Comparisons between the measured and the simulated results are conducted for the transient triboelectric charges of the display panels.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128327421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Source of miscorrelation of product level HBM to TLP test results 产品水平HBM与TLP测试结果不相关的来源
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314743
M. Prabhu, Jian-Hsing Lee, M. Natarajan, Vasantha Kumar, Ruchil Jain, T. Tsai, Liao Zhiqing, Dominic Thurmer
{"title":"Source of miscorrelation of product level HBM to TLP test results","authors":"M. Prabhu, Jian-Hsing Lee, M. Natarajan, Vasantha Kumar, Ruchil Jain, T. Tsai, Liao Zhiqing, Dominic Thurmer","doi":"10.1109/EOSESD.2015.7314743","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314743","url":null,"abstract":"Correlation between TLP and HBM test results at product level and/or complex ESD circuit is not feasible. In product level HBM testing there can be stress condition which is worse at low current compared to high ESD current. Such results cannot be replicated in TLP.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132406763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
ESD and disturbance cases in electrostatic protected areas 静电保护区内的静电及干扰情况
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314792
P. Tamminen, T. Viheriakoski, L. Ukkonen, L. Sydanheimo
{"title":"ESD and disturbance cases in electrostatic protected areas","authors":"P. Tamminen, T. Viheriakoski, L. Ukkonen, L. Sydanheimo","doi":"10.1109/EOSESD.2015.7314792","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314792","url":null,"abstract":"Electrostatic protected area (EPA) can effectively prevent ESD failures from charged operators, work benches and tools. However, electrical disturbances and ESD events from other sources can still exist in well-built EPAs. In this paper failures found in electronic assembly environments are analyzed to improve coverage of ESD control programs.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126074322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Self-ESD-protected transmission line broadband in CMOS28nm UTBB-FDSOI 基于CMOS28nm UTBB-FDSOI的自防静电传输线宽带
2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2015-11-02 DOI: 10.1109/EOSESD.2015.7314805
J. Bourgeat, T. Lim, B. Heitz, J. Jimenez, P. Galy
{"title":"Self-ESD-protected transmission line broadband in CMOS28nm UTBB-FDSOI","authors":"J. Bourgeat, T. Lim, B. Heitz, J. Jimenez, P. Galy","doi":"10.1109/EOSESD.2015.7314805","DOIUrl":"https://doi.org/10.1109/EOSESD.2015.7314805","url":null,"abstract":"Advanced CMOS Technologies, and particularly Ultra-Thin Body and BOX Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology provide good performances for analog high frequency and ultra-low power applications. We present in this paper self-ESD-protected transmission lines based on two different ESD strategies. Specific ESD protections based on bidirectional SCR (bi-SCR) are directly embedded on the transmission lines.","PeriodicalId":341383,"journal":{"name":"2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116737607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书