2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)最新文献

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Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments 基于有限元模拟和实验的晶圆级CSP应力分析与设计优化
S. Rzepka, E. Hofer, J. Simon, E. Meusel, H. Reichl
{"title":"Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments","authors":"S. Rzepka, E. Hofer, J. Simon, E. Meusel, H. Reichl","doi":"10.1109/ECTC.2001.927810","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927810","url":null,"abstract":"A design assessment and optimization process for wafer-level CSPs is demonstrated. Besides the basic design, the thermal stress in WLCSPs with underfill and with increased standoff height, respectively, are analyzed by FEM simulations. The results are validated and a lifetime model is calibrated by experiments. Afterwards, a WLCSP with stacked balls is optimized using the FEM models. Its total gain in lifetime over the basic design is estimated to reach 780%. WLCSP with optimum underfill even endure 10 and 20 times longer than the basic WLCSPs. Soft underfill, however, has almost no effect on the critical inelastic strain. In addition to these practical results, the paper discusses some of the risks of FEM models (such as the singularity problem) and proposes ways of avoiding or overcoming them.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122132715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Study on mobility of water and polymer chain in epoxy for microelectronic applications 微电子用环氧树脂中水和聚合物链的迁移性研究
S. Luo, J. Leisen, C. Wong
{"title":"Study on mobility of water and polymer chain in epoxy for microelectronic applications","authors":"S. Luo, J. Leisen, C. Wong","doi":"10.1109/ECTC.2001.927710","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927710","url":null,"abstract":"This paper presents a study on mobility of water and polymer chain in epoxy materials. Solid state nuclear magnetic resonance (NMR) techniques (both /sup 1/H NMR and /sup 2/H NMR) were used to study the binding states of water within two epoxy formulations along with the possible plasticizing effects of moisture affecting the mobility of polymer chains. Absorbed water reduces the glass transition temperature of polymeric material. However, the presence of moisture has no significant effect on the polymer chain mobility at temperatures below the reduced glass transition temperature. Water in an epoxy in its rubbery state above the glass transition has a much higher mobility than in a polymer in its glassy state. The mobility of water absorbed by a polymer in its rubbery state is similar to that of pure water. The translational mobility of water within epoxies was studied by measuring the diffusion coefficient of water in epoxies through the water uptake. Higher rotational mobilities of water and polymer chains in the rubbery state lead to a significant increase of the water diffusion coefficient in the rubbery state polymer matrix as compared to a polymer in its glassy state.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122154556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Creep behavior of a molding compound and its effect on packaging process stresses 一种成型化合物的蠕变行为及其对包装过程应力的影响
M. S. Kiasat, G.Q. Zhang, L. Ernst, G. Wisse
{"title":"Creep behavior of a molding compound and its effect on packaging process stresses","authors":"M. S. Kiasat, G.Q. Zhang, L. Ernst, G. Wisse","doi":"10.1109/ECTC.2001.927907","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927907","url":null,"abstract":"Critically high thermal stresses are induced in the constituents of an electronic package during packaging processes, due to the mismatch of the thermal expansion/contraction of the constituents. These stresses may cause cracks in the silicon die in some package configurations. The temperature-dependent creep behavior of an epoxy molding (packaging) compound is studied here in order to analyze the stresses induced in the packaging processes reliably. Isothermal one-day creep experiments are performed at different temperatures ranging from 24.5/spl deg/C to 175/spl deg/C (above the glass transition temperature of the compound). Significant creep behavior of the epoxy compound is observed even at room temperature. The tensile creep compliance and the increasing time-dependent Poisson's ratio of the material at different temperatures are successfully used to construct viscoelastic master curves for these material properties. It is observed that the shift factor of the compound cannot be fitted by the well-known WLF equation. Further, the viscoelastic model of the material is implemented in a finite element program and verified by means of the results of a creep test that is performed at a non-isothermal condition. Moreover, the effect of the creep behavior of the molding compound on the packaging process stress field and its evolution is investigated. Finally substantial cost saving is realized by package design optimization based on the reliable prediction of the packaging process stresses.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125488470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Improved VCSEL structures for 10 gigabit-Ethernet and next generation optical-integrated PC-boards 改进了用于10千兆以太网和下一代光集成pc板的VCSEL结构
F. Mederer, R. Jager, J. Joos, M. Kicherer, R. King, R. Michalzik, M. Riedl, H. Unold, K. Ebeling, S. Lehmacher, B. Wittmann, A. Neyer
{"title":"Improved VCSEL structures for 10 gigabit-Ethernet and next generation optical-integrated PC-boards","authors":"F. Mederer, R. Jager, J. Joos, M. Kicherer, R. King, R. Michalzik, M. Riedl, H. Unold, K. Ebeling, S. Lehmacher, B. Wittmann, A. Neyer","doi":"10.1109/ECTC.2001.927657","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927657","url":null,"abstract":"We have investigated direct optical interconnection between processor ICs on chip-to-chip level using VCSELs and 2-D 17 cm long, 120 /spl mu/m diameter step-index polymer optical fiber (POF) bundles. Their bandwidth-length-product of 2 GHz/spl middot/m makes them well suited for low-cost high-speed parallel optical interconnects on a board level. We have demonstrated 10 Gbit/s PRBS NRZ data transmission over four channels of a POF array.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128239673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
High speed multichip modules using flip chip mount technology for 10 Gbps optical transmission systems 采用倒装芯片安装技术的高速多芯片模块,用于10gbps光传输系统
K. Takahashi, T. Ikeuchi, T. Tsuda, T. Chuzenji
{"title":"High speed multichip modules using flip chip mount technology for 10 Gbps optical transmission systems","authors":"K. Takahashi, T. Ikeuchi, T. Tsuda, T. Chuzenji","doi":"10.1109/ECTC.2001.927929","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927929","url":null,"abstract":"This Paper describes small-sized multichip modules (MCMs) for 10 Gbps optical transmission systems. We have developed three kinds of MCMs. MCMs include LSIs we have newly developed by employing SiGe bipolar process. Each kind of MCM is composed of an alumina substrate with flat lead frames, LSIs mounted by flip chip mount technology, passive SMT components, and a heat spreader. To achieve wide-band characteristics of MCMs, the grounded coplanar waveguide design is adopted for the transmission lines on MCMs. The heat spreader is attached to the backside of each LSI through thermally conductive silicone compound for highly effective cooling. These MCMs have been applied for our 10 Gbps optical transmitter and receiver modules in the wavelength division multiplexing (WDM) system, and achieved 1.6 Tbps (10 Gbps/spl times/160 channels) of transmission capacity.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116599455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterization of lead-free solders and under bump metallurgies for flip-chip package 倒装芯片封装用无铅焊料和凹凸冶金的特性
Jong-Kai Lin, A. de Silva, D. Frear, Yifan Guo, Jin-wook Jang, Li Li, D. Mitchell, B. Yeung, C. Zhang
{"title":"Characterization of lead-free solders and under bump metallurgies for flip-chip package","authors":"Jong-Kai Lin, A. de Silva, D. Frear, Yifan Guo, Jin-wook Jang, Li Li, D. Mitchell, B. Yeung, C. Zhang","doi":"10.1109/ECTC.2001.927767","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927767","url":null,"abstract":"A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121317905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Radiative coupling in BGA packaging for mixed-signal and high-speed digital 混合信号和高速数字BGA封装中的辐射耦合
W. Woods, E. Diaz-Alvarez, J. Krusius
{"title":"Radiative coupling in BGA packaging for mixed-signal and high-speed digital","authors":"W. Woods, E. Diaz-Alvarez, J. Krusius","doi":"10.1109/ECTC.2001.927775","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927775","url":null,"abstract":"Mixed signal packaging must provide high levels of isolation between analog, RF and digital partitions. This has in the past been done on the subsystem level. Future mixed-signal systems should provide this isolation on the package-level and, possibly even on the chip-level. Here we study package-level isolation, focusing on circuit and radiative coupling mechanisms in the ball-grid-array (BGA) environment. Double printed-wiring-board (PWB) test structures joined with BGA solder balls have been designed and fabricated. We have simulated full-wave coupling using 3D FEM simulation and circuit coupling using circuit simulation with 2D capacitance and inductance matrices. Time-domain coupling measurements on unshielded and shielded coupling structures have been performed and correlated with simulations. Based on this we have developed an understanding of circuit and radiative coupling in the BGA environment. Techniques to manage mixed-signal BGA isolation have been identified.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"27 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120873892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The impact of split power planes on package performance 分离电源平面对封装性能的影响
J.R. Miller
{"title":"The impact of split power planes on package performance","authors":"J.R. Miller","doi":"10.1109/ECTC.2001.927963","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927963","url":null,"abstract":"The purpose of this study is to assess the impact of the split power planes on package performance. A non-custom package with 16 power plane splits is studied from the perspective of plane noise, trace impedance and trace crosstalk. 2D and 3D simulations are performed on the package using selected sections of the package. The plane noise is found not to be significant when there is either low or high driver transient current demand. In the low current demand case, current is primarily confined to the region of the plane beneath the trace and the transient plane voltage is small. In the high current demand case, guidelines are given to minimize the impact of the split planes. Among these guidelines, a minimum trace to plane split distance should be maintained such that the effective inductance is not increased. 2D simulations are performed to examine the impact of the split plane on the signal trace impedance. Signal trace impedance is found to vary depending on its proximity to the plane split. The impact of the plane splits on the signal trace crosstalk is investigated. Capacitive coupling between traces is reduced by distancing the signal trace from the plane split. 3D simulations using a subsection of the multiple split plane package are performed. Plots showing the near end and far end crosstalk for five traces distributed about a plane split are included. Crosstalk is found not to increase for traces bordering the plane split as long as a minimum trace to plane split distance is maintained.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116460836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Impact of JEDEC test conditions on new-generation package reliability JEDEC测试条件对新一代封装可靠性的影响
L. Mercado, B. Chavez
{"title":"Impact of JEDEC test conditions on new-generation package reliability","authors":"L. Mercado, B. Chavez","doi":"10.1109/ECTC.2001.927701","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927701","url":null,"abstract":"JEDEC Standard has been widely used in the electronic industry to qualify package performance under temperature and humidity conditions. Demands for high packaging density of low pin-count packages have driven the development of a new generation of packages to replace the Quad Flat Packages (QFP). Package size has been reduced drastically. Package reflow temperature has been considerably higher due to the application of lead-free solder. Consequently, the JEDEC standard testing on these packages needs to be re-evaluated. In this paper, moisture diffusion analysis, heat transfer analysis, as well as an interface fracture mechanics-based thermomechanical analysis have been conducted. The impact of different reflow profiles was investigated. Due to the smaller package size and higher reflow temperature, the new packages are more sensitive to the reflow parameters such as peak temperature and cooling rate. For the reliability testing of the new-generation packages, modification of the JEDEC standards may be necessary to ensure that these packages are not subjected to more stringent criteria than their previous counterparts.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131153033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Evaluation and optimization of package processing, design, and reliability through solder joint profile prediction 通过焊点轮廓预测对封装工艺、设计和可靠性进行评估和优化
B. Yeung, T. Lee
{"title":"Evaluation and optimization of package processing, design, and reliability through solder joint profile prediction","authors":"B. Yeung, T. Lee","doi":"10.1109/ECTC.2001.927906","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927906","url":null,"abstract":"Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133665692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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