The impact of split power planes on package performance

J.R. Miller
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引用次数: 10

Abstract

The purpose of this study is to assess the impact of the split power planes on package performance. A non-custom package with 16 power plane splits is studied from the perspective of plane noise, trace impedance and trace crosstalk. 2D and 3D simulations are performed on the package using selected sections of the package. The plane noise is found not to be significant when there is either low or high driver transient current demand. In the low current demand case, current is primarily confined to the region of the plane beneath the trace and the transient plane voltage is small. In the high current demand case, guidelines are given to minimize the impact of the split planes. Among these guidelines, a minimum trace to plane split distance should be maintained such that the effective inductance is not increased. 2D simulations are performed to examine the impact of the split plane on the signal trace impedance. Signal trace impedance is found to vary depending on its proximity to the plane split. The impact of the plane splits on the signal trace crosstalk is investigated. Capacitive coupling between traces is reduced by distancing the signal trace from the plane split. 3D simulations using a subsection of the multiple split plane package are performed. Plots showing the near end and far end crosstalk for five traces distributed about a plane split are included. Crosstalk is found not to increase for traces bordering the plane split as long as a minimum trace to plane split distance is maintained.
分离电源平面对封装性能的影响
本研究的目的是评估分割电源平面对封装性能的影响。从平面噪声、走线阻抗和走线串扰的角度研究了一种具有16路功率平面分叉的非定制封装。使用所述包装的选定部分对所述包装进行2D和3D模拟。当驱动瞬态电流需求低或高时,平面噪声都不显著。在低电流需求情况下,电流主要局限于走线下方的平面区域,瞬态平面电压很小。在高电流需求的情况下,给出指导方针,以尽量减少分割平面的影响。在这些准则中,应保持最小走线到平面的分离距离,以使有效电感不增加。进行了二维仿真,以检验分离平面对信号走线阻抗的影响。发现信号走线阻抗随其与平面分裂的接近程度而变化。研究了平面分裂对信号走线串扰的影响。通过将信号走线与平面分路隔离,可以减少走线之间的电容耦合。使用多分割平面包的一个分段进行了三维模拟。图显示了近端和远端串扰的五个路径分布在一个平面分裂。只要保持最小的走线到平面分裂的距离,就不会增加与平面分裂相邻的走线的串扰。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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