2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第2页

Clock Glitch versus SIFA 时钟故障与SIFA

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250822

Aein Rezaei Shahmirzadi, A. Moradi

引用次数: 2

DFT 2020 TOC

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/dft50435.2020.9250759

引用次数: 0

Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms 嵌入式高性能计算平台上基于软件的ASIL-D汽车应用的多种冗余

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250750

S. Alcaide, Leonidas Kosmidis, Carles Hernández, J. Abella

引用次数: 11

Resistive RAM SET and RESET Switching Voltage Evaluation as an Entropy Source for Random Number Generation 作为随机数产生熵源的阻性RAM SET和RESET开关电压评估

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250726

Hussein Bazzi, J. Postel-Pellerin, H. Aziza, M. Moreau, A. Harb

引用次数: 0

[DFT 2020 Front cover] [DFT 2020封面]

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/dft50435.2020.9250775

引用次数: 0

Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL 满足TMR间距约束的高压水堆辐射硬化合法化

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250918

C. Georgakidis, C. Sotiriou

{"title":"Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL","authors":"C. Georgakidis, C. Sotiriou","doi":"10.1109/DFT50435.2020.9250918","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250918","url":null,"abstract":"Reduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening design flow differs from the standard design flow and currently suffers from insufficient industrial EDA tool support. R-Abax is an academic, Displacement-driven RADHARD legalisation algorithm, based on the Triple Modular Redundancy (TMR) technique, solely for Flip-Flops (FF). R-Abax ensures that a particle strike will only affect one FF of the TMR triplet, by enforcing minimum spacing constraints among FF triplets. Although the Displacement-driven R-Abax algorithm easily satisfies the spacing constraints, its Quality of Results (QoR) depends strongly on the QoR of the original placement. In this work, we propose an improved version of R-Abax, which considers the circuit Total Half-Perimeter Wire Length (HPWL) when evaluating cell moves. Experimental results indicate that the HPWL-driven R-Abax can achieve an improvement in Power, Performance and Area (PPA), compared to the Displacement-driven version. For the HPWL-driven R-Abax, as with the original version, larger minimum spacing constraints between triplet FFs does not significantly affect the QoR, rendering the proposed RADHARD flow attractive for achieving Transient Faults mitigation.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126027435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive Faults 通过检测门穷举故障来改进测试集以覆盖测试孔

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250778

I. Pomeranz

引用次数: 0

Latest Trends in Hardware Security and Privacy 硬件安全和隐私的最新趋势

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250816

G. D. Natale, F. Regazzoni, V. Albanese, F. Lhermet, Y. Loisel, Abderrahmane Sensaoui, S. Pagliarini

引用次数: 1

Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems 基于马尔可夫链的软实时系统有效DSE检查点与回滚恢复建模与分析

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250892

Siva Satyendra Sahoo, B. Veeravalli, Akash Kumar

{"title":"Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems","authors":"Siva Satyendra Sahoo, B. Veeravalli, Akash Kumar","doi":"10.1109/DFT50435.2020.9250892","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250892","url":null,"abstract":"Continued transistor scaling and increasing power density have led to an increase in both transient and aging-related fault-rates in silicon-based electronic systems. The use of traditional spatial redundancy-based fault-mitigation methods such as Triple Modular Redundancy (TMR) can lead to even higher power dissipation. However, in addition to accelerating the system’s rate of aging, such high power dissipation may be infeasible for resource-constrained embedded systems. Consequently, temporal redundancy-based methods are being increasingly used for satisfying embedded applications’ reliability requirements. However, such methods result in stochastic execution time and hence introduce additional complexity for soft real-time system design. A simulation-based approach for finding the quality of service (QoS)-aware optimal design points can lead to large design space exploration (DSE) time. To this end, we propose a Markov Chain-based model for checkpointing with rollback recovery, a widely used temporal redundancy-based fault-mitigation method. Specifically, a task execution using Checkpointing with intermediate validations is modeled as an absorbing Markov Chain and methods are presented for estimating the mean, variance and probability distribution of the task’s resulting execution time. Further, we propose a multilevel design space pruning approach for determining the QoS-aware configuration of Checkpointing. The presented modeling and estimation methods lead to considerable improvements in DSE time compared to a simulation-only approach.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An Emulation Platform for Evaluating the Reliability of Deep Neural Networks 深度神经网络可靠性评估的仿真平台

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250872

C. D. Sio, S. Azimi, L. Sterpone

引用次数: 7