2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献

Using digital imagers to characterize the dependence of energy and area distributions of SEUs on elevation 利用数字成像仪表征seu能量和面积分布对高程的依赖关系

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250888

G. Chapman, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Ruoyi Zhao, I. Koren, Z. Koren

{"title":"Using digital imagers to characterize the dependence of energy and area distributions of SEUs on elevation","authors":"G. Chapman, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Ruoyi Zhao, I. Koren, Z. Koren","doi":"10.1109/DFT50435.2020.9250888","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250888","url":null,"abstract":"Camera Integrated circuits (ICs) suffer from soft errors known as Single Event Upsets (SEUs). Unlike traditional ICs, camera sensors record the location and energy deposited by each SEU. Camera pixels measure when and where cosmic ray particles hit and store the deposited charge when dark-frame images are taken. Hence, with large datasets of time-lapsed dark-frame images, pixel analysis provides the intensity and energy distribution of deposited SEU charges, the energy vs occurrence rate, the total area of the charge ball, and potentially the dependence of the number of SEUs on the camera elevation. Previously developed noise distribution analysis enables the removal of noise and the detection of low energy SEUs. In addition, it allows estimating the area of the deposited charge. We used two DSLR cameras and measured SEU rates at elevations from sea level to 1088 m, allowing us to explore the dependence of SEU energy and area distributions on elevation. We observed significant increases in SEUs with elevation changes of < 50 meters.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123022009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliability Evaluation of Pruned Neural Networks against Errors on Parameters 基于参数误差的剪枝神经网络可靠性评估

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250812

Zhen Gao, Xiaohui Wei, Han Zhang, Wenshuo Li, Guangjun Ge, Yu Wang, P. Reviriego

引用次数: 11

Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits 提高扫描受限电路延迟测试覆盖的可观察性驱动路径生成

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250797

Avijit Chakraborty, D. Walker

引用次数: 2

Lightweight Fault Detection and Management for Image Restoration 面向图像恢复的轻量级故障检测与管理

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250844

C. Bolchini, Luca Cassano, A. Miele, Matteo Biasielli

{"title":"Lightweight Fault Detection and Management for Image Restoration","authors":"C. Bolchini, Luca Cassano, A. Miele, Matteo Biasielli","doi":"10.1109/DFT50435.2020.9250844","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250844","url":null,"abstract":"Image restoration is generally employed to recover an image that has been blurred, for example, for noise suppression purposes. The Richardson-Lucy (RL) algorithm is a widely used iterative approach for image restoration. In this paper we propose a lightweight application-specific fault detection and management scheme for RL that exploits two specific characteristics of such algorithm: i) there is a strong correlation between the input and output images of each iteration, and ii) the algorithm is often able to produce a final output that is very similar to the expected one although the output of an intermediate iteration has been corrupted by a fault. The proposed scheme exploits these characteristics to detect the occurrence of a fault without requiring duplication and to determine whether the error in the output of an intermediate iteration of the algorithm would be absorbed (thus avoiding image dropping and algorithm reexecution) or whether the image has to be discarded and the overall elaboration to be re-executed. An experimental campaign demonstrated that our scheme allows for an execution time reduction of about 54% w.r.t. the classical Duplication with Comparison (DWC), still providing about 99% fault detection.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131213663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliable Classification with Ensemble Convolutional Neural Networks 集成卷积神经网络的可靠分类

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250837

Zhen Gao, Han Zhang, Xiaohui Wei, Tong Yan, Kangkang Guo, Wenshuo Li, Yu Wang, P. Reviriego

{"title":"Reliable Classification with Ensemble Convolutional Neural Networks","authors":"Zhen Gao, Han Zhang, Xiaohui Wei, Tong Yan, Kangkang Guo, Wenshuo Li, Yu Wang, P. Reviriego","doi":"10.1109/DFT50435.2020.9250837","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250837","url":null,"abstract":"Convolutional Neural Networks (CNNs) are widely used in computer vision and natural language processing. Due to large computational requirements, implementation of CNNs on FPGAs becomes an popular option. As CNNs being used in safety critical applications, reliability become a priority. This poses challenges as FPGAs are prone to suffer soft errors. Traditional fault tolerant techniques based on modular redundancy introduce a large overhead, which may not be acceptable for many resources-limited embedded system. This paper explores the use of an ensemble of CNNs to build reliable classifiers. The idea is to combine several “weak” classifiers to obtain a “strong” one, so that the classifier can still work reliably if one of its members fails. Differently from traditional ensemble learning that looks for the classifiers to complement each other, in our case similarity is also important to achieve fault tolerance. To evaluate the potential of using ensembles to implement fault tolerant CNNs, an initial study is done on ResNets. The results show that, relative to a single deep ResNet, an ensemble of shallow ResNets could provide similar classification results while providing an effective protection against errors with limited overhead.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114808620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

DFT 2020 Committees DFT 2020委员会

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/dft50435.2020.9250804

引用次数: 0

Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems 研究辐射软误差对近似计算系统可靠性的影响

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250865

Lucas Matana Luza, D. Söderström, G. Tsiligiannis, H. Puchner, C. Cazzaniga, Ernesto Sánchez, A. Bosio, L. Dilillo

引用次数: 13

Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations 忆阻互补电阻开关传感:建模与仿真

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250843

V. Gupta, D. Pellegrini, S. Khandelwal, A. Jabir, Shahar Kvatinsky, E. Martinelli, C. Natale, M. Ottavi

引用次数: 0

A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications 用于高度安全应用的轻量级可重构随机存储器PUF

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250829

Basma Hajri, Mohammad M. Mansour, A. Chehab, H. Aziza

{"title":"A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications","authors":"Basma Hajri, Mohammad M. Mansour, A. Chehab, H. Aziza","doi":"10.1109/DFT50435.2020.9250829","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250829","url":null,"abstract":"Recently, the variability of resistive memory devices (RRAM) has become an attractive feature for hardware security in the form of a Physically Unclonable Function (PUF). Although several RRAM-based PUFs have appeared in the literature, they still suffer from some issues related to reliability, reconfigurability, and extensive integration cost. This paper presents a novel lightweight reconfigurable RRAM-based PUF (LRR-PUF) wherein multiple RRAM cells, connected to the same bit line and same transistor (1T4R), are used to generate a single bit response. The pulse programming method used is also innovative and exploits variations in the number of pulses needed to switch the RRAM cell as the primary entropy source of the PUF. The main feature of the proposed PUF is its integration with any RRAM architecture at almost no additional cost. Through extensive simulations, including the impact of temperature and voltage variations along with statistical characterization, we demonstrate that the LRR-PUF exhibits such attractive properties including high reliability (almost 100%), reconfigurability, uniqueness, cost, and efficiency.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121377087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A novel Network-on-Chip security algorithm for tolerating Byzantine faults 一种新的容忍拜占庭故障的片上网络安全算法

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI: 10.1109/DFT50435.2020.9250906

Soultana Ellinidou, G. Sharma, O. Markowitch, G. Gogniat, J. Dricot

{"title":"A novel Network-on-Chip security algorithm for tolerating Byzantine faults","authors":"Soultana Ellinidou, G. Sharma, O. Markowitch, G. Gogniat, J. Dricot","doi":"10.1109/DFT50435.2020.9250906","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250906","url":null,"abstract":"Since the number of processors and cores on a single chip is increasing, the interconnection among them becomes significant. Network-on-Chip (NoC) has direct access to all resources and information within a System-on-Chip (SoC), rendering it appealing to attackers. Malicious attacks targeting NoC are a major cause of performance depletion and they can cause arbitrary behavior of links or routers, that is, Byzantine faults. Byzantine faults have been thoroughly investigated in the context of Distributed systems however not in Very Large Scale Integration (VLSI) systems. Hence, in this paper we propose a novel fault model followed by the design and implementation of lightweight algorithms, based on Software Defined Network-on-Chip (SDNoC) architecture. The proposed algorithms can be used to build highly available NoCs and can tolerate Byzantine faults. Additionally, a set of different scenarios has been simulated and the results demonstrate that by using the proposed algorithms the packet loss decreases between 65% and 76% under Transpose traffic, 67% and 77% under BitReverse and 55% and 66% under Uniform traffic.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127740762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1