通过在微编程硬件加速器中使用测试微程序来减少DFT硬件开销

Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Z. Navabi
{"title":"通过在微编程硬件加速器中使用测试微程序来减少DFT硬件开销","authors":"Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Z. Navabi","doi":"10.1109/DFT50435.2020.9250763","DOIUrl":null,"url":null,"abstract":"Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implementation. The reloadable microinstructions in a microprogrammed architecture provide an opportunity for self-testing of the accelerator by a test microprogram. This paper describes a mechanism of testing microprogrammed accelerators of an embedded system. We utilize the accelerator microinstructions to test the datapath and controller of our existing home-grown accelerator, called iMPAC. For prototyping, this architecture is implemented on an FPGA and its testing is compared with a hard-wired controller utilizing scan and other standard test techniques.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator\",\"authors\":\"Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Z. Navabi\",\"doi\":\"10.1109/DFT50435.2020.9250763\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implementation. The reloadable microinstructions in a microprogrammed architecture provide an opportunity for self-testing of the accelerator by a test microprogram. This paper describes a mechanism of testing microprogrammed accelerators of an embedded system. We utilize the accelerator microinstructions to test the datapath and controller of our existing home-grown accelerator, called iMPAC. For prototyping, this architecture is implemented on an FPGA and its testing is compared with a hard-wired controller utilizing scan and other standard test techniques.\",\"PeriodicalId\":340119,\"journal\":{\"name\":\"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT50435.2020.9250763\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT50435.2020.9250763","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

由于许多机器学习应用程序在执行过程中存在大量的重复计算和并发性,基于可重构加速器的嵌入式硬件架构已经成为一种方便高效的硬件实现手段。微程序结构中的可重新加载微指令为测试微程序对加速器进行自我测试提供了机会。本文介绍了一种嵌入式系统微程序加速器的测试机制。我们利用加速器微指令来测试我们现有的国产加速器iMPAC的数据路径和控制器。对于原型设计,该架构在FPGA上实现,并将其测试与利用扫描和其他标准测试技术的硬连线控制器进行比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator
Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implementation. The reloadable microinstructions in a microprogrammed architecture provide an opportunity for self-testing of the accelerator by a test microprogram. This paper describes a mechanism of testing microprogrammed accelerators of an embedded system. We utilize the accelerator microinstructions to test the datapath and controller of our existing home-grown accelerator, called iMPAC. For prototyping, this architecture is implemented on an FPGA and its testing is compared with a hard-wired controller utilizing scan and other standard test techniques.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信