Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator

Abstract

Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implementation. The reloadable microinstructions in a microprogrammed architecture provide an opportunity for self-testing of the accelerator by a test microprogram. This paper describes a mechanism of testing microprogrammed accelerators of an embedded system. We utilize the accelerator microinstructions to test the datapath and controller of our existing home-grown accelerator, called iMPAC. For prototyping, this architecture is implemented on an FPGA and its testing is compared with a hard-wired controller utilizing scan and other standard test techniques.