Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Z. Navabi
{"title":"Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator","authors":"Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Z. Navabi","doi":"10.1109/DFT50435.2020.9250763","DOIUrl":null,"url":null,"abstract":"Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implementation. The reloadable microinstructions in a microprogrammed architecture provide an opportunity for self-testing of the accelerator by a test microprogram. This paper describes a mechanism of testing microprogrammed accelerators of an embedded system. We utilize the accelerator microinstructions to test the datapath and controller of our existing home-grown accelerator, called iMPAC. For prototyping, this architecture is implemented on an FPGA and its testing is compared with a hard-wired controller utilizing scan and other standard test techniques.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT50435.2020.9250763","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implementation. The reloadable microinstructions in a microprogrammed architecture provide an opportunity for self-testing of the accelerator by a test microprogram. This paper describes a mechanism of testing microprogrammed accelerators of an embedded system. We utilize the accelerator microinstructions to test the datapath and controller of our existing home-grown accelerator, called iMPAC. For prototyping, this architecture is implemented on an FPGA and its testing is compared with a hard-wired controller utilizing scan and other standard test techniques.