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2011 9th East-West Design & Test Symposium (EWDTS)最新文献

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Overview of the prototyping technologies for Actel® RTAX-S FPGAs Actel®RTAX-S fpga原型技术概述
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116422
O. Melnikova
{"title":"Overview of the prototyping technologies for Actel® RTAX-S FPGAs","authors":"O. Melnikova","doi":"10.1109/EWDTS.2011.6116422","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116422","url":null,"abstract":"High reliability and nonvolatile antifuse technology make Actel RTAX-S the FPGA of choice for space designers. As correct functionality of such designs is crucial, prototyping becomes an important step of the verification flow. As RTAX-S FPGAs are one-time programmable, prototyping can become challenging. This paper provides an overview and comparison of the existing approaches to prototyping of Actel RTAX-S FPGAs.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128920860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Designing power supply (PS) using digital PID based on AVR microcontrollers 基于AVR单片机的数字PID电源设计
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116593
T. Mohamadi
{"title":"Designing power supply (PS) using digital PID based on AVR microcontrollers","authors":"T. Mohamadi","doi":"10.1109/EWDTS.2011.6116593","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116593","url":null,"abstract":"This paper presents a method to design a kind of power supply (PS) using PID (Proportional, Integral, and Derivative) controller. AVR microcontroller, atmega16 has been used in designing PS. Nowadays most of industrials systems use microcontrollers. PS is the integral part in each of them. A good idea is using these processors in order to generate the needed power for other parts of the systems. Especially the appearance of microcontroller with too many facilities such as; timer, counter, interrupt, and so forth can help to use them more effectively. PID controllers are used widely in industry and they have proved their helpfulness. Designed PS uses digital PID that has been designed with too many facilities in AVR microcontroller. This kind of PS is in small size. Likewise, it can be compacted to be used in portable devices such as mobile or lap top chargers. Their efficiency is higher than usual linear power supplies. It will be more effective for systems with high demanded power rather than with low power, because in high level power there is no need to use transformer and the whole size of the system will be reduced.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130157222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation by the special formula of an arbitrary subset of code words of (m, n)-code for designing a self-testing checker 利用(m, n)码字的任意子集的特殊公式实现了自检检查器的设计
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116599
N. Butorina, S. Ostanin
{"title":"Implementation by the special formula of an arbitrary subset of code words of (m, n)-code for designing a self-testing checker","authors":"N. Butorina, S. Ostanin","doi":"10.1109/EWDTS.2011.6116599","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116599","url":null,"abstract":"The problem of synthesis of the self-testing checker for arbitrary l code words of (m, n)-code is considered. In particular, the problem of representation of number l by the sum of cardinal numbers of subsets of the code words corresponding to essential subtrees of the tree representing all code words of (m, n)-code is investigated. The properties such essential subtries are described.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117036277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Designing an embedded system for interfacing with networks based on ARM 设计了一个基于ARM的嵌入式网络接口系统
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116598
T. Mohamadi
{"title":"Designing an embedded system for interfacing with networks based on ARM","authors":"T. Mohamadi","doi":"10.1109/EWDTS.2011.6116598","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116598","url":null,"abstract":"This paper presents a method to design a smart circuit to interface with some protocols such as RS232, USB, CAN, and the most important of all: Ethernet. The main feature in the designed circuit is using Real Time Operating System (RTOS) on ARM series 32-bit processors: LPC2478. Compared with the customary ways to control and data acquisition, the device based on the embedded system offers better features and flexibility, with an overall design for reliability, durability and ease of installation. This paper has illustrated hardware architecture and real time multi-task software process based on μC/OS-II. There are too many usages for such designed system in control and data acquisition systems. Especially, in network interfaces with different protocol layers, it can be used as a smart gateway or router and so forth. As a proof of concept, a simple system was designed to test the designed circuit.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128182976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Verification and diagnosis of SoC HDL-code SoC HDL-code的验证与诊断
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116418
V. Hahanov, Dong-Won Park, O. Guz, A. Priymak
{"title":"Verification and diagnosis of SoC HDL-code","authors":"V. Hahanov, Dong-Won Park, O. Guz, A. Priymak","doi":"10.1109/EWDTS.2011.6116418","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116418","url":null,"abstract":"Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132541228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On experimental research of efficiency of tests construction for combinational circuits by the focused search method 聚焦搜索法提高组合电路测试构建效率的实验研究
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116588
V. Kulikov, V. V. Mokhor
{"title":"On experimental research of efficiency of tests construction for combinational circuits by the focused search method","authors":"V. Kulikov, V. V. Mokhor","doi":"10.1109/EWDTS.2011.6116588","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116588","url":null,"abstract":"Consider the possibility reducing the iteration value in building complete validation tests for digital devices. Building a test for a given fault is reduced to searching the terminal node in the signals assignment tree. The reducing is achieved by accumulating and using of information about dead-end conditions to avoid similar situations in the earlier stages. Allows any faults that can be described by logical functions.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116413205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design fault injection-based technique and tool for FPGA projects verification 基于故障注入的FPGA项目验证技术和工具
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116608
L. Reva, Vitaliy Kulanov, V. Kharchenko
{"title":"Design fault injection-based technique and tool for FPGA projects verification","authors":"L. Reva, Vitaliy Kulanov, V. Kharchenko","doi":"10.1109/EWDTS.2011.6116608","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116608","url":null,"abstract":"Design fault injection-based technique (DBIT) is proposed to implement a procedure of independent verification. The possible options of the proposed DBIT application are presented. The developed design fault profiling and injection tool is described. It is given an example of fault profiling and injection carrying out by the developed tool.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124891861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
About dependability in cyber-physical systems 关于网络物理系统的可靠性
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116428
L. Miclea, T. Sanislav
{"title":"About dependability in cyber-physical systems","authors":"L. Miclea, T. Sanislav","doi":"10.1109/EWDTS.2011.6116428","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116428","url":null,"abstract":"This paper presents definitions characterizing the concepts regarding cyber-physical systems and dependability. Cyber-physical systems incorporate computing, communication and storage capabilities with monitoring and/or control of entities in the physical world in a dependably, securely, efficiently and real-time way. The challenges of cyber-physical system research are concerning: real-time system abstractions; robustness, safety and security; QoS composition; and nor least dependability. Dependability is first introduced as a global concept that subsumes the usual attributes of reliability, availability, safety, integrity and maintainability. The paper aims to define research challenges to achieve the dependability in cyber-physical hydropower systems. The significant challenge of the dependability in cyber-physical hydropower systems is evaluation of the system behavior in terms of interdependencies between cyber and physical components of the system.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125182343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
Maintaining uniformity in the processes of encryption and decryption with a variable number of encryption rounds 使用可变的加密轮数保持加密和解密过程的一致性
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116574
Lukasz Smolinski
{"title":"Maintaining uniformity in the processes of encryption and decryption with a variable number of encryption rounds","authors":"Lukasz Smolinski","doi":"10.1109/EWDTS.2011.6116574","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116574","url":null,"abstract":"Article presents modification for the cryptographic hardware accelerators. Modification, which allows for add new functionality to cryptography systems. Functionality allows for the dynamic changes in the number of rounds with maintaining uniformity in the processes of encryption and decryption. The proposed modification was discussed on DES algorithm example.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123131087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Methodology of the pre-silicon verification of the processor core 处理器核的预硅验证方法
2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI: 10.1109/EWDTS.2011.6116581
S. Berdyshev, V. Boykov, Y. Gimpilevich, Yuri Iskiv, Gilad Keren, Denis Muratov, Igor Smirnov, V. Vertegel
{"title":"Methodology of the pre-silicon verification of the processor core","authors":"S. Berdyshev, V. Boykov, Y. Gimpilevich, Yuri Iskiv, Gilad Keren, Denis Muratov, Igor Smirnov, V. Vertegel","doi":"10.1109/EWDTS.2011.6116581","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116581","url":null,"abstract":"Practical experience of pre-silicon verification of the processor core is presented. The proposed methodology gives good results, good coverage, and requires a short verification time period.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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