SoC HDL-code的验证与诊断

2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI:10.1109/EWDTS.2011.6116418

V. Hahanov, Dong-Won Park, O. Guz, A. Priymak

{"title":"SoC HDL-code的验证与诊断","authors":"V. Hahanov, Dong-Won Park, O. Guz, A. Priymak","doi":"10.1109/EWDTS.2011.6116418","DOIUrl":null,"url":null,"abstract":"Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Verification and diagnosis of SoC HDL-code\",\"authors\":\"V. Hahanov, Dong-Won Park, O. Guz, A. Priymak\",\"doi\":\"10.1109/EWDTS.2011.6116418\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.\",\"PeriodicalId\":339676,\"journal\":{\"name\":\"2011 9th East-West Design & Test Symposium (EWDTS)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-09-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 9th East-West Design & Test Symposium (EWDTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2011.6116418\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 9th East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2011.6116418","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

提出了向量逻辑空间中对象关系的xor矩阵和结构测试模型。开发了用于验证和诊断hdl代码功能故障的基于断言的模型和方法，从而可以大大缩短软件和硬件的上市时间。提出了一种用于嵌入式诊断的多矩阵精简逻辑指令集处理器的体系结构模型。

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Verification and diagnosis of SoC HDL-code

Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.

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2011 9th East-West Design & Test Symposium (EWDTS)

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