聚焦搜索法提高组合电路测试构建效率的实验研究

2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI:10.1109/EWDTS.2011.6116588

V. Kulikov, V. V. Mokhor

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引用次数: 0

摘要

考虑在为数字设备构建完整的验证测试时减少迭代值的可能性。针对给定故障构建测试简化为在信号分配树中搜索终端节点。减少是通过积累和使用关于死角条件的信息来实现的，以避免在早期阶段出现类似的情况。允许任何可以用逻辑函数描述的故障。

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On experimental research of efficiency of tests construction for combinational circuits by the focused search method

Consider the possibility reducing the iteration value in building complete validation tests for digital devices. Building a test for a given fault is reduced to searching the terminal node in the signals assignment tree. The reducing is achieved by accumulating and using of information about dead-end conditions to avoid similar situations in the earlier stages. Allows any faults that can be described by logical functions.

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2011 9th East-West Design & Test Symposium (EWDTS)

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