2006 IEEE Compound Semiconductor Integrated Circuit Symposium最新文献

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Characterization and Modeling of Wire Bond Interconnects up to 100 GHz 高达100ghz的线键互连的表征和建模
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319915
D. Jahn, R. Reuter, Yi Yin, J. Feige
{"title":"Characterization and Modeling of Wire Bond Interconnects up to 100 GHz","authors":"D. Jahn, R. Reuter, Yi Yin, J. Feige","doi":"10.1109/CSICS.2006.319915","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319915","url":null,"abstract":"This paper presents a model for single and multiple wire bond interconnects for the frequency range from 200 MHz up to 100 GHz, usable in agilents advanced design system (ADS). Test structures for on-wafer s-parameter characterization have been developed. Equivalent circuits for single- and multiple wire bond connections are derived, respectively. The small-signal elements of the equivalent circuit are based on physical parameters and scalable with the bond wire distance and length. The model demonstrates an excellent agreement with measurements in broad frequency range","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132108923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Carbon Nanotube Based Memory Using CMOS Production Techniques 基于CMOS技术的碳纳米管存储器
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319875
R.F. Smith, T. Rueckes, S. Konsek, J. Ward, D. K. Brock, B. Segal
{"title":"Carbon Nanotube Based Memory Using CMOS Production Techniques","authors":"R.F. Smith, T. Rueckes, S. Konsek, J. Ward, D. K. Brock, B. Segal","doi":"10.1109/CSICS.2006.319875","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319875","url":null,"abstract":"Manufacturability of most electronic devices based on carbon nanotubes depends on the ability to place, manipulate, and control individual structures at the molecular level. This approach is problematic due to the precise placement and registration required thus making large scale manufacturing difficult if not impossible. A novel technique has been developed to overcome this hurdle, allowing CNT based nanodevices to be fabricated directly on existing production CMOS fabrication lines. This technique has been demonstrated in a Class 1 commercial fab and enables the fabrication of CNT non-volatile memory devices. This unique approach relies on the deposition and lithographic patterning, using standard semiconductor toolsets, of a 1-2 nm thick fabric of nanotubes which retain their molecular scale electro-mechanical characteristics, even when patterned to less than 100 nm feature sizes. The non-volatile CNT switch is turned on using electrostatic forces and remains in the on state through van der Waals (VDW) attraction. The switch is turned off by overcoming the VDW forces and creating separation of the tubes from a contact. The resulting devices are free from metallic or material contaminants and particulates. Because these non-volatile memory elements are created in an all thin-film process, they are easily integrated directly within existing CMOS circuitry to facilitate addressing and readout. Devices fabricated on a commercial line and integrated with transistors have been switched successfully both as single bits and in arrays. Devices have been switched over 50 million times without failure - continued testing is underway. Write and erase voltages can be less than 5 V and can scale downwards with smaller geometries. Additionally, the switch has been tested and shown to switch in less than 3 ns. Design consideration, device structure, testing, and reliability data are presented","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116682434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-quality InAlN/GaN high electron mobility transistors on Si (111) by metalorganic chemical vapor deposition 金属有机化学气相沉积法在Si(111)上制备高电子迁移率的InAlN/GaN晶体管
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319948
N. Watanabe, H. Yokoyama, M. Hiroki, Y. Oda, T. Kobayashi, T. Yagi
{"title":"High-quality InAlN/GaN high electron mobility transistors on Si (111) by metalorganic chemical vapor deposition","authors":"N. Watanabe, H. Yokoyama, M. Hiroki, Y. Oda, T. Kobayashi, T. Yagi","doi":"10.1109/CSICS.2006.319948","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319948","url":null,"abstract":"We successfully fabricated high-quality InAlN/GaN heterostructures for high electron mobility transistors (HEMTs) on Si (111) substrate by metalorganic chemical vapor deposition (MOCVD). X-ray diffraction measurements revealed that InAlN/GaN heterostructures grown under optimal conditions have a flat surface and an abrupt heterointerface. The surface roughness evaluated from atomic force microscopy (AFM) is improved, compared with previous reports. Electron mobility of about 1,200 and over 1,800 cm2/V-s are obtained for InAlN/GaN heterostructures without and with an AlN interlayer, respectively. These mobility values are the highest ones ever reported for InAlN/GaN heterostructures grown on Si substrates","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121728398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Broadband Dual-Gate Balanced Low Noise Amplifiers 宽带双栅平衡低噪声放大器
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319888
W. Deal, M. Biedenbender, P. Liu, C. Namba, S. Chen, M. Sergant, J. Uyeda, M. Siddiqui, R. Lai, B. Allen
{"title":"Broadband Dual-Gate Balanced Low Noise Amplifiers","authors":"W. Deal, M. Biedenbender, P. Liu, C. Namba, S. Chen, M. Sergant, J. Uyeda, M. Siddiqui, R. Lai, B. Allen","doi":"10.1109/CSICS.2006.319888","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319888","url":null,"abstract":"In this paper, we present three MMIC low noise amplifiers using dual-gate GaAs HEMT devices in a balanced amplifier configuration. The designs target three different frequency bands including 5-9 GHz, 9-18 GHz and 20-40 GHz. These dual-gate balanced designs demonstrate the excellent qualities of balanced amplifiers in terms of bandwidth, matched characteristics and bandwidth, but demonstrate higher bandwidth than designs with a single-stage common-source device. Additionally, noise performance is excellent, with the 5-9 GHz LNA demonstrating <1.75-dB NF, the 9-18 GHz LNA <2.75-dB NF and the 20-40 GHz LNA <2.5 dB NF. Demonstrating high gain and excellent bandwidth, the dual-gate devices seem a logical choice for the balanced amplifier topology","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127939185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High Voltage and High Switching Frequency Power-Supplies using a GaN-HEMT 使用GaN-HEMT的高压和高开关频率电源
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319947
W. Saito, I. Omura, T. Domon, K. Tsuda
{"title":"High Voltage and High Switching Frequency Power-Supplies using a GaN-HEMT","authors":"W. Saito, I. Omura, T. Domon, K. Tsuda","doi":"10.1109/CSICS.2006.319947","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319947","url":null,"abstract":"This paper reports 13.56 MHz and 27.1 MHz class-E amplifiers with a high voltage GaN-HEMT as the main switching device showing the possibility of GaN-HEMTs in high frequency switching power applications such as RF power-supply applications. The 380 V/1.9 A GaN power-HEMT was designed and fabricated for high-voltage power electronics applications. The demonstrated 13.56 MHz circuit achieved the output power of 13.4 W and the power efficiency of 91 % under a drain-peak voltage as high as 330 V. For a 27.1 MHz circuit, the output power was 13.8 W with the efficiency of 89.6 %. These results show that high voltage GaN-devices are suitable for high frequency switching applications under high DC input voltages of over 100 V","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122252649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
5W GaN MMIC for Millimeter-Wave Applications 5W GaN MMIC毫米波应用
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319922
K. Boutros, W. Luo, Y. Ma, G. Nagy, J. Hacker
{"title":"5W GaN MMIC for Millimeter-Wave Applications","authors":"K. Boutros, W. Luo, Y. Ma, G. Nagy, J. Hacker","doi":"10.1109/CSICS.2006.319922","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319922","url":null,"abstract":"Power amplifier MMICs were designed and fabricated using micro-strip topology on 3-mil thinned semi-insulating SiC substrates with through vias. A two-stage 50-ohm matched Ka-band MMIC with an output-stage composed of a 1.2-mm-wide device operated with Psat of 5 Watts at 26.5 GHz, corresponding to a power density of 3.1 W/mm, with an associated gain of 9dB and a PAE of 20%. The MMIC produced 13 plusmn1dB of linear gain from 25GHz to 30GHz with an associated P3dB of > 3 watts across the band. These results are the best combination of output power and power density reported from a Ka-band GaN MMIC to date","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132396794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Quick Thermal Evaluation Software for GaAs Power MESFET's GaAs功率MESFET的快速热评估软件
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319927
D. S. Rawal, A. Dhanotia
{"title":"Quick Thermal Evaluation Software for GaAs Power MESFET's","authors":"D. S. Rawal, A. Dhanotia","doi":"10.1109/CSICS.2006.319927","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319927","url":null,"abstract":"Two analytical solutions for calculating thermal resistance are studied and a MATLAB based quick thermal evaluation software is developed to calculate thermal parameters of GaAs based power MESFET with known geometrical parameters. The software computes thermal resistance and channel temperature and also generates contour plots for temperature profiles along the surface and substrate of the FET. The thermal parameter estimation was revalidated on commercially available GaAs power device from commercial foundry and the valves of thermal resistance and channel temperature are in close agreement with the practically measured values. The software requires minimal computing resources and capable of running on any platform which supports MATLAB. The software can be used during the initial process of device development for deriving some critical conclusions important for efficient device heat management","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130171403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Fully Matched Ku-band 9W PHEMT MMIC High Power Amplifier 全匹配ku波段9W PHEMT MMIC高功率放大器
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319887
C. Lin, H.Z. Liu, C. Chu, H. Huang, Y. Wang, C. Liu, C. Chang, C. Wu, C. Chang
{"title":"A Fully Matched Ku-band 9W PHEMT MMIC High Power Amplifier","authors":"C. Lin, H.Z. Liu, C. Chu, H. Huang, Y. Wang, C. Liu, C. Chang, C. Wu, C. Chang","doi":"10.1109/CSICS.2006.319887","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319887","url":null,"abstract":"A 9 watt AlGaAs/InGaAs/GaAs PHEMT MMIC power amplifier for Ku band applications is presented. This two-stage amplifier with chip size of 11.12 mm2 (4.52 mm times 2.46 mm) is designed to fully match 50 ohm input and output impedance. With 8 volts and 900 mA DC bias condition, 12 dB small signal gain, 39.5 dBm (9 Watt) saturated output power with 30% power-added efficiency from 14 to 14.2 GHz can be achieved. This high power amplifier also achieved the best power densities (809 mW/ mm2) at Ku band reported to date","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126739856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A Ka-band Monolithic Doubly-Balanced Mixer 一个ka波段单片双平衡混频器
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319880
C. Lin, Chi-Ming Lin, Jui‐Chieh Chiu, T. Tsai, Yeong-Her Wang
{"title":"A Ka-band Monolithic Doubly-Balanced Mixer","authors":"C. Lin, Chi-Ming Lin, Jui‐Chieh Chiu, T. Tsai, Yeong-Her Wang","doi":"10.1109/CSICS.2006.319880","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319880","url":null,"abstract":"A 26-38 GHz monolithic doubly balanced mixer is presented. In this design, a novel configuration was employed to have wide band performance while keeping compact size and simple IF extraction. The MMIC was implemented with WIN 0.15 mum PHEMT process and the chip size is 1 times 2.5 mm2. This mixer has a conversion loss of better than 6 dB with good port-to-port isolation and a DC-10 GHz IF bandwidth","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124639539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Frequency Scaling and Topology Comparison of Millimeter-wave CMOS VCOs 毫米波CMOS压控振荡器的频率缩放与拓扑比较
2006 IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2006-11-01 DOI: 10.1109/CSICS.2006.319873
K. W. Tang, S. Leung, N. Tieu, P. Schvan, S. Voinigescu
{"title":"Frequency Scaling and Topology Comparison of Millimeter-wave CMOS VCOs","authors":"K. W. Tang, S. Leung, N. Tieu, P. Schvan, S. Voinigescu","doi":"10.1109/CSICS.2006.319873","DOIUrl":"https://doi.org/10.1109/CSICS.2006.319873","url":null,"abstract":"This paper presents an algorithmic design methodology and frequency scaling technique for CMOS VCOs. It illustrates the almost ideal scaling of a fundamental 10-GHz, 90-nm CMOS Colpitts VCO with -117 dBc/Hz phase noise and 4 dBm output power to 77 GHz. The 77-GHz VCO features linear 8.3% tuning range and a phase noise of -100.3 dBc/Hz at 1 MHz offset. The first complementary cross-coupled VCO operating at 77 GHz is also reported. In addition, a new figure of merit for CMOS VCO based on the one defined in the 2003 ITRS is proposed to adequately account for the VCO output power and efficiency","PeriodicalId":338151,"journal":{"name":"2006 IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121815982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
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