2015 IEEE International Electron Devices Meeting (IEDM)最新文献_第7页

Single suspended InGaAs nanowire MOSFETs 单悬浮InGaAs纳米线mosfet

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409808

C. Zota, L. Wernersson, E. Lind

引用次数: 17

A two-gap capacitive structure for high aspect-ratio capacitive sensor arrays 一种用于高宽高比电容式传感器阵列的双间隙电容结构

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409725

Y. Tang, K. Najafi

引用次数: 4

A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications 坚固的晶圆薄化至2.6 μm，适用于无凹凸互连和DRAM WOW应用

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409653

Y. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto, A. Kawai, K. Arai, T. Ohba

引用次数: 18

150 GHz FMAX with high drain breakdown voltage immunity by multi gate oxide dual work-function (MGO-DWF)-MO SFET 采用多栅极氧化物双工作功能(MGO-DWF)-MO场效应晶体管，具有高抗漏击穿电压的150 GHz FMAX

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409769

T. Miyata, H. Tanaka, K. Kagimoto, M. Kamiyashiki, M. Kamimura, A. Hidaka, M. Goto, K. Adachi, A. Hokazono, T. Ohguro, K. Nagaoka, Y. Watanabe, S. Hirooka, Y. Ito, S. Kawanaka, K. Ishimaru

{"title":"150 GHz FMAX with high drain breakdown voltage immunity by multi gate oxide dual work-function (MGO-DWF)-MO SFET","authors":"T. Miyata, H. Tanaka, K. Kagimoto, M. Kamiyashiki, M. Kamimura, A. Hidaka, M. Goto, K. Adachi, A. Hokazono, T. Ohguro, K. Nagaoka, Y. Watanabe, S. Hirooka, Y. Ito, S. Kawanaka, K. Ishimaru","doi":"10.1109/IEDM.2015.7409769","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409769","url":null,"abstract":"We propose Multi Gate Oxide - Dual Work-Function (MGO-DWF)-MOSFET which is suitable for low power AB-class RF power amplifier (RF PA). This was examined for the first time by comparing with a standard Cascode connection circuitry composed of LV- and HVMOSFETs. Dramatically improved FMAX (150 GHz) with sufficient drain break-down voltage (VBD) was experimentally confirmed in a practical device structure. MGO-DWF-MOSFET has multiple roles in a unit device such as LV-MOSFET in source side regions and HV-MOSFET in drain side regions. This distinctive structure enables the reduction of the device area and a gate capacitance (CG) with a higher transconductance (GM) and the suppression of drain conductance (GDS). Enhancement of FMAX, in other words, DC operation current reduction is achieved at a given operation point. This indicates that MGO-DWF MOSFET is advantageous for low power amplifier circuitry applications, typically for RF PA in internet of things (IoT) products.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128176402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Predictive compact modeling of random variations in FinFET technology for 16/14nm node and beyond 16/14nm及以上节点FinFET技术随机变化的预测紧凑建模

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409787

Xiaobo Jiang, Xingsheng Wang, Runsheng Wang, B. Cheng, A. Asenov, Ru Huang

引用次数: 29

First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 μS/μm in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters 首次演示Ge纳米线CMOS电路:最低SS为64 mV/dec，最高gmax为1057 μS/μm, Ge CMOS逆变器最大电压增益为54 V/V

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409610

Heng Wu, Wangran Wu, M. Si, P. Ye

引用次数: 41

High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology 基于集成扇出(InFO)晶圆级封装技术的毫米波系统集成的高性能无源器件

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409763

C. Tsai, J. Hsieh, Wei-Heng Lin, L. Yen, J. Hung, T. Peng, Hsi-Ching Wang, Cheng-Yu Kuo, I.L. Huang, W. Chu, Yi-Yang Lei, C. H. Yu, L. Sheu, C. Hsieh, C. S. Liu, K. Yee, Chuei-Tang Wang, Doug C. H. Yu

引用次数: 11

Germanium-based transistors for future high performance and low power logic applications 基于锗的晶体管用于未来的高性能和低功耗逻辑应用

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409613

Y. Yeo, X. Gong, M. V. van Dal, G. Vellianitis, M. Passlack

{"title":"Germanium-based transistors for future high performance and low power logic applications","authors":"Y. Yeo, X. Gong, M. V. van Dal, G. Vellianitis, M. Passlack","doi":"10.1109/IEDM.2015.7409613","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409613","url":null,"abstract":"High mobility channel materials could replace strained Si to enhance speed performance and/or reduce power consumption in future transistors. Ge has the highest hole mobility among common elemental and compound semiconductors, and an electron mobility that is two times larger than that of Si. Ge is thus a promising channel material for future CMOS (Fig. 1). Key challenges include cost-effective integration of Ge on Si in a manufacturable process, formation of high-quality gate stack on Ge for n- and p-FETs at aggressively scaled EOTs that deliver high channel mobilities, and leakage issues related to its small bandgap. In this paper, we discuss recent research progress in advancing Ge-based transistor technologies. Integration of Ge on Si substrate to enable fabrication of high performance devices and formation of high-quality gate stack for Ge FETs (particularly for n-FETs) will be discussed. We also explore opportunities to boost the mobility of Ge, e.g. by incorporating Sn in Ge to form Ge1-xSnx. Furthermore, by raising the Sn composition, the band gap EG of Ge1-xSnx becomes smaller and transits from indirect to direct, making Ge1-xSnx a promising material for tunneling transistors.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130206909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Gate-first high-k/metal gate DRAM technology for low power and high performance products 栅极优先的高k/金属栅极DRAM技术，用于低功耗和高性能产品

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409775

M. Sung, S. Jang, Hyunjin Lee, Y. Ji, Jae-Il Kang, Tae-Oh Jung, T. Ahn, Y. Son, Hyungchul Kim, Sun-Woo Lee, Seungmin Lee, Jung-Hak Lee, S. Baek, Eun-Hyup Doh, Heung-Jae Cho, T. Jang, I. Jang, Jae-Hwan Han, Kyung-Bo Ko, Yu-Jun Lee, Su-Bum Shin, Jae-Seon Yu, S. Cho, Ji-Hye Han, Dong-Kyun Kang, Jinsung Kim, Jae-Sang Lee, Keundo Ban, S. Yeom, H. Nam, Dong-Kyu Lee, M. Jeong, Byungil Kwak, Jeongsoo Park, K. Choi, Sung-Kye Park, N. Kwak, Sung-Joo Hong

{"title":"Gate-first high-k/metal gate DRAM technology for low power and high performance products","authors":"M. Sung, S. Jang, Hyunjin Lee, Y. Ji, Jae-Il Kang, Tae-Oh Jung, T. Ahn, Y. Son, Hyungchul Kim, Sun-Woo Lee, Seungmin Lee, Jung-Hak Lee, S. Baek, Eun-Hyup Doh, Heung-Jae Cho, T. Jang, I. Jang, Jae-Hwan Han, Kyung-Bo Ko, Yu-Jun Lee, Su-Bum Shin, Jae-Seon Yu, S. Cho, Ji-Hye Han, Dong-Kyun Kang, Jinsung Kim, Jae-Sang Lee, Keundo Ban, S. Yeom, H. Nam, Dong-Kyu Lee, M. Jeong, Byungil Kwak, Jeongsoo Park, K. Choi, Sung-Kye Park, N. Kwak, Sung-Joo Hong","doi":"10.1109/IEDM.2015.7409775","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409775","url":null,"abstract":"It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La2O3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129760369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Oxide-based RRAM: Requirements and challenges of modeling and simulation 基于氧化物的RRAM:建模和仿真的需求和挑战

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409634

Jinfeng Kang, B. Gao, Peng Huang, Haitong Li, Yudi Zhao, Zheng Chen, Changze Liu, L. Liu, X. Liu

引用次数: 21