A two-gap capacitive structure for high aspect-ratio capacitive sensor arrays

This paper presents a two-gap CMOS-compatible technology to fabricate very tall (>500μm) 3D high aspect-ratio (HAR) silicon structures with narrow HAR sensing gaps (<;5μm) to achieve high sensitivity in capacitive sensors. This technology is especially suited for forming capacitive MEMS sensor arrays and offers the following advantages: 1) hundreds or thousands of small-footprint high-sensitivity devices can be integrated on a single chip to provide multiplicity of functions (greater dynamic range, fault-tolerance, reconfigurability, etc.); and 2) the ability to integrate MEMS devices on top of CMOS circuitry perform local signal processing for individual elements in the array. We designed, fabricated and tested capacitive accelerometer arrays in 1mm thick silicon using this technology, and demonstrated 8X increase in capacitive sensitivity thanks to the narrow HAR gaps, increased transduction area, increased device height (larger proof-mass), and reduced spring stiffness.