Proceedings Design, Automation and Test in Europe Conference and Exhibition最新文献_第8页

Using BDDs and ZBDDs for efficient identification of testable path delay faults 利用bdd和zbdd对可测试路径延迟故障进行有效识别

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268826

Saravanan Padmanaban, S. Tragoudas

引用次数: 10

A low power strategy for future mobile terminals 未来移动终端的低功耗策略

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268938

Mladen Nikitovic, M. Brorsson

引用次数: 3

Tuning in-sensor data filtering to reduce energy consumption in wireless sensor networks 调整传感器内数据滤波以降低无线传感器网络的能耗

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268992

I. Kadayif, M. Kandemir

引用次数: 27

Scan power minimization through stimulus and response transformations 扫描功率最小化通过刺激和响应转换

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268880

O. Sinanoglu, A. Orailoglu

{"title":"Scan power minimization through stimulus and response transformations","authors":"O. Sinanoglu, A. Orailoglu","doi":"10.1109/DATE.2004.1268880","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268880","url":null,"abstract":"Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force SOC designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133606543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

A new approach to timing analysis using event propagation and temporal logic 一种利用事件传播和时间逻辑进行时间分析的新方法

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269055

Arijit Mondal, P. Chakrabarti, C. Mandal

{"title":"A new approach to timing analysis using event propagation and temporal logic","authors":"Arijit Mondal, P. Chakrabarti, C. Mandal","doi":"10.1109/DATE.2004.1269055","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269055","url":null,"abstract":"Present day designers require deep reasoning methods to analyze circuit timing. This includes analysis of effects of dynamic behavior (like glitches) on critical paths, simultaneous switching and identification of specific patterns and their timings. This paper proposes a novel approach that uses a combination of symbolic event propagation and temporal reasoning to extract timing properties of gate-level circuits. The formulation captures complex situations like triggering of traditional false paths and simultaneous switching in a unified symbolic representation in addition to identifying false paths, critical paths as well as conditions for such situations. This information is then represented as an event-time graph. A simple temporal logic on events is proposed that can be used to formulate a wide class of useful queries for various input scenarios. These include maximum/minimum delays, transition times, duration of patterns, etc. An algorithm is developed that retrieves answers to such queries from the event-time graph. A complete BDD based implementation of this system has been made. Results on the ISCAS85 benchmarks indicate very interesting properties of these circuits.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133773454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

/spl times/pipesCompiler: a tool for instantiating application specific networks on chip /spl times/pipesCompiler:一个在芯片上实例化应用特定网络的工具

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268999

A. Jalabert, S. Murali, L. Benini, G. Micheli

{"title":"/spl times/pipesCompiler: a tool for instantiating application specific networks on chip","authors":"A. Jalabert, S. Murali, L. Benini, G. Micheli","doi":"10.1109/DATE.2004.1268999","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268999","url":null,"abstract":"Future systems on chips (SoCs) will integrate a large number of processor and storage cores onto a single chip and require networks on chip (NoC) to support the heavy communication demands of the system. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication infrastructure should optimally match communication patterns among these components accounting for the individual component needs. In this paper we present /spl times/pipesCompiler, a tool for automatically instantiating an application-specific NoC for heterogeneous multi-processor SoCs. The /spl times/pipesCompiler instantiates a network of building blocks from a library of composable soft macros (switches, network interfaces and links) described in SystemC at the cycle-accurate level. The network components are optimized for that particular network and support reliable, latency-insensitive operation. Example systems with application-specific NoCs built using the /spl times/pipesCompiler show large savings in area (factor of 6.5), power (factor of 2.4) and latency (factor of 1.42) when compared to a general-purpose mesh-based NoC architecture.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116620063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 243

System-level performance analysis in SystemC SystemC中的系统级性能分析

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268876

H. Posadas, F. Herrera, P. Sánchez, E. Villar, Francisco Blasco

{"title":"System-level performance analysis in SystemC","authors":"H. Posadas, F. Herrera, P. Sánchez, E. Villar, Francisco Blasco","doi":"10.1109/DATE.2004.1268876","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268876","url":null,"abstract":"As both the ITRS and the Medea+ DA Roadmaps have highlighted, early performance estimation is an essential step in any SoC design methodology based on International Technology Roadmap for Semiconductors (2001) and The MEDEA+ Design Automation Roadmap (2002). This paper presents a C++ library for timing estimation at system level. The library is based on a general and systematic methodology that takes as input the original SystemC source code without any modification and provides the estimation parameters by simply including the library within a usual simulation. As a consequence, the same models of computation used during system design are preserved and all simulation conditions are maintained. The method exploits the advantages of dynamic analysis, that is, easy management of unpredictable data-dependent conditions and computational efficiency compared with other alternatives (ISS or RT simulation, without the need for SW generation and compilation and HW synthesis). Results obtained on several examples show the accuracy of the method. In addition to the fundamental parameters needed for system-level design exploration, the proposed methodology allows the designer to include capture points at any place in the code. The user can process the corresponding captured events for unrestricted timing constraint verification.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117005244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 61

Efficient implementations of mobile video computations on domain-specific reconfigurable arrays 针对特定领域可重构阵列的移动视频计算的高效实现

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269064

S. Khawam, S. Baloch, A. Pai, Imran Ahmed, N. Aydin, T. Arslan, F. Westall

引用次数: 13

A new optimized implementation of the SystemC engine using acyclic scheduling 使用无循环调度的SystemC引擎的新优化实现

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268903

D. G. Pérez, Gilles Mouchard, O. Temam

{"title":"A new optimized implementation of the SystemC engine using acyclic scheduling","authors":"D. G. Pérez, Gilles Mouchard, O. Temam","doi":"10.1109/DATE.2004.1268903","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268903","url":null,"abstract":"SystemC is rapidly gaining wide acceptance as a simulation framework for SoC and embedded processors. While its main assets are modularity and the very fact it is becoming a de facto standard, the evolution of the SystemC framework (from version 0.9 to version 2.0.1) suggests the environment is particularly geared toward increasing the framework functionalities rather than improving simulation speed. For cycle-level simulation, speed is a critical factor as simulation can be extremely slow, affecting the extent of design space exploration. In this article, we present a fast SystemC engine that, in our experience, can speed up simulations by a factor of 1.93 to 3.56 over SystemC 2.0.1. This SystemC engine is designed for cycle-level simulators and for the moment, it only supports the subset of the SystemC syntax (signals, methods) that is most often used for such simulators. We achieved greater speed (1) by completely rewriting the SystemC engine and improving the implementation software engineering, and (2) by proposing a new scheduling technique, intermediate between SystemC dynamic scheduling technique and existing static scheduling schemes. Unlike SystemC dynamic scheduling, our technique removes many if not all useless process wake-ups, while using a simpler scheduling algorithm than in existing static scheduling techniques.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115074123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

Building the hierarchy from a flat netlist for a fast and accurate post-layout simulation with parasitic components 从平面网表构建层次结构，用于快速准确的寄生组件布局后仿真

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269268

P. Daglio, D. Iezzi, Danilo Rimondi, C. Roma, Salvatore Santapa

{"title":"Building the hierarchy from a flat netlist for a fast and accurate post-layout simulation with parasitic components","authors":"P. Daglio, D. Iezzi, Danilo Rimondi, C. Roma, Salvatore Santapa","doi":"10.1109/DATE.2004.1269268","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269268","url":null,"abstract":"Main concerns related to post-layout simulation, today, are about the format of the netlist coming out from the parasitic extractor. In fact, such a netlist is usually flat so that readability, whether compared to the pre-layout hierarchical one, is very poor due to device and net names which often change and to the difficulty to compare pre-layout and post-layout output signals. Furthermore, simulating such large flat netlists is frequently time consuming because it is not possible to exploit algorithms like hierarchical array reduction (HAR) and isomorphic matching (IM), strength points of state-of-the-art full chip simulators. In this paper, we present a new approach that, starting from a flat netlist with parasitic components and a pre-layout hierarchical one, allows to create a fully hierarchical post-layout netlist containing device parameters and parasitic components directly extracted from the layout. In this way, a fast and accurate post-layout simulation is made possible by the use of look-up table simulators, taking advantages from the HAR and IM algorithms as mentioned before. This methodology has been integrated in a complete design flow to guarantee first silicon success, cut down time-to-design, improve time-to-market and streamline design quality.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115133464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4