Using BDDs and ZBDDs for efficient identification of testable path delay faults

Saravanan Padmanaban, S. Tragoudas
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引用次数: 10

Abstract

We present a novel framework to identify all the robustly testable and untestable path delay faults in a circuit. The method uses a combination of decision diagrams for manipulating path delay faults and Boolean functions. The approach benefits from processing partial paths or fanout free segments in the circuit rather than the entire path. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology identifies 350% more testable faults in the ISCAS'85 benchmark C6288 than any existing technique by utilizing only a fraction of the time compared to earlier work.
利用bdd和zbdd对可测试路径延迟故障进行有效识别
我们提出了一种新的框架来识别电路中所有鲁棒可测试和不可测试的路径延迟故障。该方法使用决策图和布尔函数的组合来处理路径延迟故障。该方法的优点是处理电路中的部分路径或无扇出段,而不是处理整个路径。实验证明了该框架的有效性。可以观察到,该方法在ISCAS'85基准C6288中识别的可测试故障比任何现有技术多350%,与早期工作相比,只利用了一小部分时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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