Proceedings Design, Automation and Test in Europe Conference and Exhibition最新文献

{"title":"DFY/DFM - design for yield and manufacturability (industrial tutorial)","authors":"A. Ripp, R. Sommer, E. Hennig, M. Pronath","doi":"10.1109/DATE.2004.1268807","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268807","url":null,"abstract":"Summary form only given, as follows. The tutorial presents an introduction into \"DfY/DfM - Design for Yield and Manufacturability\" covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment. Intended audience: analogue- and mixed-signal circuit designers, CAD- and design-support engineers (library management, technology migration and design reuse, process characterisation)","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125538506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The coming of age of reconfigurable computing-potentials and challenges of a new technology [Tutorial]","authors":"W. Najjar, F. Kurdahi, K. Vissers","doi":"10.1109/DATE.2004.1268810","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268810","url":null,"abstract":"Addresses modelling for analysis and optimisation of MPSoC architectures including hardware and software layers such as drivers, run-time systems and application APIs. Different scheduling strategies, communication behaviours and performance requirements must be matched and combined on a single system. 4. Presents the DELI experience to show that application level software development can be overlapped with the development of the rest of the system. DELI is aimed to generating portable HdS taking into account real-time constraints and low-level interactions with OS and the HW during early prototyping. Platforms that combine CPUs with a reconfigurable fabric on the same chip have been recently introduced. Such devices are ideally suited for many application domains ranging from multimedia to communication. A major challenge to their wider use is the lack of high level programming and design space exploration tools. This tutorial focuses on three aspects of this emerging technology: (1) the intrinsic potential of the temporal/spatial paradigm (2) The wide range of architectures, fine and coarse grained, and the trade-offs between performance and flexibility. (3) A survey of current and future applications in multimedia and mobile communication and analysis of their performance and energy requirements. It is intended for an audience of developers and researchers in high-end embedded systems. The tutorial presents methods for reliable system design. We consider systems realised on a single chip, systems consisting of several integrated components (possibly components off-the shelf-COTS), and distributed systems. We address both hardware (computation and communication) and software aspects of reliable system design. This tutorial is intended for researchers in EDA, system/chip designers and software developers for integrated systems, as well as for managers who want to learn about reliable design and how this area evolved in view of the current technology trends. The tutorial covers a spectrum of diagnosis and debug topics from the basic concepts to future challenges, over the life-cycle of a product. Established diagnosis procedures fault dictionaries, post-test fault simulation, and hardware-based backtracking will be discussed, followed by recent enhancements and advanced diagnosis topics, including methods for locating defects, approximation techniques for identifying unmodelled faults, deductive analysis, Iddq-based diagnosis, diagnosis for delay-faults, scan-chain diagnosis, BIST-based diagnosis, and design-for-diagnosability techniques. The tutorial then will focus on silicon debug techniques, design-for-debug techniques, and applications to yield improvement. Successful diagnosis methods used in real industrial products, industrial experiences, and case studies will be presented in this tutorial. determined to find out where those puzzling …","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122437882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliable design: a system perspective [Tutorial]","authors":"G. De Micheli, R. Iyer","doi":"10.1109/DATE.2004.1268811","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268811","url":null,"abstract":"Addresses modelling for analysis and optimisation of MPSoC architectures including hardware and software layers such as drivers, run-time systems and application APIs. Different scheduling strategies, communication behaviours and performance requirements must be matched and combined on a single system. 4. Presents the DELI experience to show that application level software development can be overlapped with the development of the rest of the system. DELI is aimed to generating portable HdS taking into account real-time constraints and low-level interactions with OS and the HW during early prototyping. Platforms that combine CPUs with a reconfigurable fabric on the same chip have been recently introduced. Such devices are ideally suited for many application domains ranging from multimedia to communication. A major challenge to their wider use is the lack of high level programming and design space exploration tools. This tutorial focuses on three aspects of this emerging technology: (1) the intrinsic potential of the temporal/spatial paradigm (2) The wide range of architectures, fine and coarse grained, and the trade-offs between performance and flexibility. (3) A survey of current and future applications in multimedia and mobile communication and analysis of their performance and energy requirements. It is intended for an audience of developers and researchers in high-end embedded systems. The tutorial presents methods for reliable system design. We consider systems realised on a single chip, systems consisting of several integrated components (possibly components off-the shelf-COTS), and distributed systems. We address both hardware (computation and communication) and software aspects of reliable system design. This tutorial is intended for researchers in EDA, system/chip designers and software developers for integrated systems, as well as for managers who want to learn about reliable design and how this area evolved in view of the current technology trends. The tutorial covers a spectrum of diagnosis and debug topics from the basic concepts to future challenges, over the life-cycle of a product. Established diagnosis procedures fault dictionaries, post-test fault simulation, and hardware-based backtracking will be discussed, followed by recent enhancements and advanced diagnosis topics, including methods for locating defects, approximation techniques for identifying unmodelled faults, deductive analysis, Iddq-based diagnosis, diagnosis for delay-faults, scan-chain diagnosis, BIST-based diagnosis, and design-for-diagnosability techniques. The tutorial then will focus on silicon debug techniques, design-for-debug techniques, and applications to yield improvement. Successful diagnosis methods used in real industrial products, industrial experiences, and case studies will be presented in this tutorial. determined to find out where those puzzling …","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116297663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Programming models for multiprocessor SoC (full-day) [Tutorial]","authors":"A. Jerraya, F. Pospiech, R. Ernst, G. Desoli","doi":"10.1109/DATE.2004.1268809","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268809","url":null,"abstract":"The tutorial presents an introduction into “DfY/DfM Design for Yield and Manufacturability” covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123873723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modern design techniques with systemC [Tutorial]","authors":"M. Speitel, B. Niemann, A. Braun, K. Einwich, C. Haubelt, F. Mayer","doi":"10.1109/DATE.2004.1268817","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268817","url":null,"abstract":"Summary form only given, as follows. Even with new design languages coming up, SystemC is widely accepted by EDA companies and used in many design teams. The tutorial gives an extensive overview of the application of SystemC for various aspects of system-on-chip design. It starts with an introduction to SystemC 2.0. Modelling at different levels of abstraction - from system development down to a synthesisable ASIC implementation - are covered. The tutorial is extended by HW/SW partitioning methodologies using SystemC, and includes analogue and mixed analogue/digital modelling with SystemC AMS. The verification of hardware dependent software and the novel SystemC verification library and its usage are also presented. Intended audience: This master course is targeted to designers, who want to acquire basic knowledge of SystemC and its applications as well as design managers, searching for an inside view on the usage of SystemC in a C/C++ based design flow.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126583607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Structured CAD: technology closure for modern ASICs [Tutorial]","authors":"L. Stok, J. Koehl","doi":"10.1109/DATE.2004.1268808","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268808","url":null,"abstract":"The tutorial presents an introduction into “DfY/DfM Design for Yield and Manufacturability” covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129982149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Identification and modelling of nonlinear dynamic behaviour in analogue circuits","authors":"Xiaoling Huang, H. Mantooth","doi":"10.1109/DATE.2004.1268889","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268889","url":null,"abstract":"This paper presents a new approach for identifying nonlinear dynamic behaviour in analogue circuits. The approach facilitates the creation of models that more accurately reflect the dynamic behaviour of a circuit. It has been used in a fully automated, behavioural modelling tool, Ascend, that starts from the netlist description of the circuit and generates differential algebraic equation (DAE) based behavioural models. The underlying modelling approach is overviewed to provide a context for this research. Some demonstrative test results illustrate the effectiveness of the new method.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131316676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Constraint and integer programming techniques and tools for digital system design [Tutorial]","authors":"M. Milano, K. Kuchkinski, J. Puget","doi":"10.1109/DATE.2004.1268815","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268815","url":null,"abstract":"The purpose of this master class is to present to the Digital System Design community a set of effective techniques for solving large scale combinatorial optimisation problems related to hardware and software co-design. In general, these problems are faced by modelling and solving them via Integer Programming (IP) techniques. Recently, Constraint Programming (CP) has emerged as a powerful programming paradigm that can be used in alternative or in conjunction with Integer Programming. Constraint Programming integrated concepts from different areas such as Artificial Intelligence, Mathematical Programming, Networks and Computational Logic. Its main strength concerns its efficiency, simplicity and flexibility. In particular flexibility is fundamental for changing the problem model adding or removing constraints without changing the solver. In the master class we 1) focus on finite domain Constraint Programming and its integration with Integer Programming, 2) describe system level design applications modelled via Constraint Programming 3) present ILOG, a leading edge, commercial tool embedding both Linear and Constraint Programming solvers. The objective of this master class is that of describing how emerging design methodologies for RTL power optimisation have found their way into commercial EDA tools, and how such tools have been successfully exploited in industry-strength designs. The course is organised into three main sections. The first one provides a review of the most effective RTL power optimisation techniques currently available. The second part is dedicated to the presentation and demonstration of innovative commercial EDA tools that implement the surveyed estimation and optimisation techniques. The third part reports on industrial experience on the usage of the methodologies and tools introduced in the previous sections. Intended audience for this class includes designers and design team managers from semiconductor companies and system houses, R&D engineers from EDA companies, and academic researchers and Ph.D. students in the field of IC/system design.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128487724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Balanced excitation and its effect on the fortuitous detection of dynamic defects","authors":"Jennifer Dworak, Brad Cobb, James Wingfield, M. R. Mercer","doi":"10.1109/DATE.2004.1269034","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269034","url":null,"abstract":"Dynamic defects are less likely to be fortuitously detected than static defects because they have more stringent detection requirements. We show that (in addition to more site observations) balanced excitation is essential for detection of these defects, and we present a metric for estimating this degree of balance. We also show that excitation balance correlates with the parameter /spl tau/ in the MPG-D defective part level model.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115645849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":".NET framework - a solution for the next generation tools for system-level modeling and simulation","authors":"J. Lapalme, E. Aboulhamid, G. Nicolescu, L. Charest, F. Boyer, J. David, G. Bois","doi":"10.1109/DATE.2004.1268952","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268952","url":null,"abstract":"Nowadays, the use of system level description languages is mandatory for the efficient design of complex systems. These description languages are exemplified by SystemC and SystemVerilog. In this paper, we propose a new .NET framework based system level modeling and simulation environment called Esys.NET (embedded systems design with .NET). It allows (1) cooperation - by enabling Web-based design and multi-language features, (2) easy systems specification task - by enabling integration of software components running application and operating systems and by alleviating memory management, (3) link to automatic refinement tools - by enabling translation of specification models into a standard intermediate format and annotation of specification models, and (4) comparative performances with existing environments.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123099052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}