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2013 IEEE International Conference of Electron Devices and Solid-state Circuits最新文献

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A high self-resonant and quality factor transformer using novel geometry for silicon based RFICs 一种高自谐振和质量因数变压器，采用新颖的几何形状用于硅基rfic
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628223
Hua-Bin Zhang, M. Cai, Xiao-Yong He, Gui-Hui Chen, Haijun Wu
{"title":"A high self-resonant and quality factor transformer using novel geometry for silicon based RFICs","authors":"Hua-Bin Zhang, M. Cai, Xiao-Yong He, Gui-Hui Chen, Haijun Wu","doi":"10.1109/EDSSC.2013.6628223","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628223","url":null,"abstract":"A novel 24-sided concave-convex geometry monolithic transformer that has high self-resonant frequency and quality factor is presented. It is implemented with the top level thick Cu metal and multiple geometrical structures in 0.13 um CMOS mixed-signal 1P6M salicide back-end process. Compared to those with conventional square, hexagonal and octagonal geometry structure, the novel transformer achieves better quality factor, self-resonant frequency and less chip area. The simulation results show that 1.12, 1 and 0.58 GHz improvements in SRF, and 2.4, 0.9 and 0.3 enhancements in quality factor are obtained respectively when compared to typical square, hexagonal and octagonal transformer with the same inductance of the primary and secondary winding.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133015335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-gate pHEMT modeling for high-power operation 高功率工作的多栅极pHEMT建模
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628227
Cejun Wei, Yu Zhu, D. Bartle
{"title":"Multi-gate pHEMT modeling for high-power operation","authors":"Cejun Wei, Yu Zhu, D. Bartle","doi":"10.1109/EDSSC.2013.6628227","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628227","url":null,"abstract":"Multi-gate pHEMTs are key elements in switch circuits in wireless communication applications due to their low loss and high power capacity with relatively small sizes. A great concern on their high power operation is the power step-back at on-state and at certain power level with harmonics deteriorated. In this paper we discuss the mechanism of power step-back. The power that can pass through an on-state pHEMT is dependent on saturation current, or the maximum available channel current. A premature power step-back or gain collapse in a multi-gate pHEMT is due to largely reduced saturation channel current caused by self-heating in center gate or gates. We developed a self-heating thermal model for multi-gate pHEMTs that can predict power level at that the power step-back and related hysteresis occur.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133832929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Split-output miller-compensated two-stage amplifiers 分路输出米勒补偿两级放大器
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628234
Min Tan, W. Ki
{"title":"Split-output miller-compensated two-stage amplifiers","authors":"Min Tan, W. Ki","doi":"10.1109/EDSSC.2013.6628234","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628234","url":null,"abstract":"In this paper we identify the defining characteristic of a class of split-output miller-compensated (SOM) amplifiers. Existing amplifiers implementing this defining feature are identified, and new two-stage SOM amplifiers are proposed. Various transistor-level implementations of SOM amplifiers are designed in UMC130 CMOS technology and their small-signal circuits are analyzed. Simulation results show that the proposed designs outperform the simple miller-compensated two-stage amplifier in terms of both small-signal performance and large-signal performance.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130325858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
All GaN-on-Si high power module design and performance evaluation 全氮化硅高功率模块设计及性能评估
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628150
Stone Cheng, Chieh-An Wang, Po-Chien Chou, W. Chieng, E. Chang
{"title":"All GaN-on-Si high power module design and performance evaluation","authors":"Stone Cheng, Chieh-An Wang, Po-Chien Chou, W. Chieng, E. Chang","doi":"10.1109/EDSSC.2013.6628150","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628150","url":null,"abstract":"This paper presents a 270-V, 56-A GaN power module with three AlN substrates are prepared for the module. Each substrate is composed of three parallel connected GaN chips which incorporates six 2-A AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) cells. The substrate layout inside the module is designed to reduce package parasitic. The devices are wire-bonded in parallel connection to increase the power rating. The packaged GaN HEMTs exhibit the pulsed drain current of 0.435 A/mm. Both DC and pulsed current-voltage (ID-VDS) characteristics are measured for different connection and sizes of devices, at various of power densities, pulse lengths, and duty factors. The other static parameters like threshold voltage and leakage currents were extracted to show how these parameters would scale as the devices are paralleled. Performance of multiple chip GaN power module package is studied. Experimental results demonstrated the ability to parallel nine GaN HEMTs die together and to verify the current sharing during the dynamic switching to attain high-current capacities.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Failure analysis of output stage due to ESD stress in submicron CMOS technology 亚微米CMOS工艺中ESD应力导致的输出级失效分析
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628165
Huang Xiaozong, Shi Jiangang, Huang Wengang, L. Fan
{"title":"Failure analysis of output stage due to ESD stress in submicron CMOS technology","authors":"Huang Xiaozong, Shi Jiangang, Huang Wengang, L. Fan","doi":"10.1109/EDSSC.2013.6628165","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628165","url":null,"abstract":"ESD failure of an operational amplifier in submicron CMOS technology is analyzed to locate the failure mechanism and re-design the protection structure in this paper. From the experimental results, the specifications related to the output stage with large size devices are degraded or exceed the qualified range. With the deep analysis of internal circuit of the chip, electrical measurement determines the failure mechanism. The protection of power rail is not robust enough for shunting the ESD current under ND and PS modes. RC+BigFET clamp is used to improve the ESD robustness of whole chip to 3500V which is qualified for most applications.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114564946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Band offsets of AlxGa1−xAs/GaAs heterojunction from atomistic first principles 基于原子第一性原理的AlxGa1−xAs/GaAs异质结带偏移
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628136
Yin Wang, F. Zahid, Y. Zhu, Lei Liu, Jian Wang, Hong Guo
{"title":"Band offsets of AlxGa1−xAs/GaAs heterojunction from atomistic first principles","authors":"Yin Wang, F. Zahid, Y. Zhu, Lei Liu, Jian Wang, Hong Guo","doi":"10.1109/EDSSC.2013.6628136","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628136","url":null,"abstract":"The properties of III-V compound semiconductors and their heterojunctions have been relentlessly investigated due to their wide-ranging applications in electronic and optoelectronic technologies. One of most important electronic property of heterojunctions is the band offset which describes the relative alignment of the electronic bands across the junction interface. Accurate determination of band offsets is critical for understanding quantum transport properties of the heterojuncton. For many III-V materials systems, the band offset has been carefully measured experimentally.[1]","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114866201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A charge pump with reduced current variation and mismatch in low-voltage low-power PLLs 在低压低功率锁相环中减少电流变化和失配的电荷泵
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628140
Jia Yaoyao, Fang Jian, Qiao Ming, Zhou Ze-kun, Yan Wentao, Zhang Bo
{"title":"A charge pump with reduced current variation and mismatch in low-voltage low-power PLLs","authors":"Jia Yaoyao, Fang Jian, Qiao Ming, Zhou Ze-kun, Yan Wentao, Zhang Bo","doi":"10.1109/EDSSC.2013.6628140","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628140","url":null,"abstract":"A charge pump with excellent current matching and negligible current variation characteristics over wide output voltage dynamic range is proposed, which is simulated in the 0.18μm standard CMOS process with the power supply 1.8V. The proposed charge pump circuit improves current matching by applying a high gain operational trans-conductance amplifier. Negligible current variation is achieved by inducing a negative feedback loop to suppress the channel modulation effect. Compared with conventional charge pump circuit, the current mismatch of the proposed charge pump circuit is less than 0.5% within the output voltage dynamic range from 0.2V to 1.7V, and the current variation is reduced to 0.8% over the output voltage dynamic range from 0.32V to 1.7V. Besides, the average power consumption of the proposed charge pump circuit is about 0.48mW making it suitable for low voltage and low power PLLs.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115851142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fabrication and characteristics of fully transparent Aluminum-doped zinc oxide thin-film transistors 全透明掺铝氧化锌薄膜晶体管的制备与特性研究
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628226
D. Shan, Dedong Han, F. Huang, Yu Tian, Suoming Zhang, Y. Cong, Yi Wang, Lifeng Liu, Xing Zhang, Shengdong Zhang
{"title":"Fabrication and characteristics of fully transparent Aluminum-doped zinc oxide thin-film transistors","authors":"D. Shan, Dedong Han, F. Huang, Yu Tian, Suoming Zhang, Y. Cong, Yi Wang, Lifeng Liu, Xing Zhang, Shengdong Zhang","doi":"10.1109/EDSSC.2013.6628226","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628226","url":null,"abstract":"Fully transparent Aluminum-doped zinc oxide (AZO) thin-film transistors (TFTs) were fabricated using radio frequency sputtering at room temperature. To ensure transparency, the AZO-TFTs were fabricated on glass substrate, with SiO2 as gate insulator. Indium tin oxide (ITO) was adopted as gate and source/drain electrodes. The electrical characteristics of AZO-TFT were investigated by IDS-VDS and IDS-VGS measurements, excellent electrical properties were obtained. Furthermore, we researched the post-annealing effects on characteristics of AZO-TFT.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121676559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design optimization of gate-all-around vertical nanowire transistors for future memory applications 面向未来存储器应用的栅极全能垂直纳米线晶体管的设计优化
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628113
T. Agarwal, O. Badami, S. Ganguly, S. Mahapatra, D. Saha
{"title":"Design optimization of gate-all-around vertical nanowire transistors for future memory applications","authors":"T. Agarwal, O. Badami, S. Ganguly, S. Mahapatra, D. Saha","doi":"10.1109/EDSSC.2013.6628113","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628113","url":null,"abstract":"This paper investigates the application of gate-all-around (GAA) vertical nanowire transistors (VNWFET) as an access element in future non-volatile memories (NVM) such as resistive random-access memory (RRAM), phase-change random access memory (PCRAM) and spin-torque-transfer memory (STT-RAM or MRAM). We primarily choose direct-current (DC) parameters ION and ION/IOFF as our figure of merit (FOM) and optimize the vertical nanowire FET by taking various critical process parameters into account such as channel length, fin doping, gate overlap, and cross-sectional shape of the nanowire transistor. Further, using the optimized device in a 3×3 cross-bar array arrangement, we evaluate the read/write disturb due to the active device on it's neighboring inactive devices. We show that the optimized access device can be used for a range of currents ratings required by different memory devices, ION being as high as 0.19 A/μm2 and IOFF being as low as 2 nA/μm2.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121393519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Sound monitoring based wireless healthcare and a typical implmenation for heart rate monitoring 基于无线医疗保健的声音监测和心率监测的典型实现
2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI: 10.1109/EDSSC.2013.6628160
Zhihua Wang, Kai Yang, Wan Wang, Hanjun Jiang, Shouhao Wu, Qingliang Lin, Wen Jia
{"title":"Sound monitoring based wireless healthcare and a typical implmenation for heart rate monitoring","authors":"Zhihua Wang, Kai Yang, Wan Wang, Hanjun Jiang, Shouhao Wu, Qingliang Lin, Wen Jia","doi":"10.1109/EDSSC.2013.6628160","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628160","url":null,"abstract":"This paper proposes a wireless healthcare system architecture that uses a wearable smart sensor to record the body sounds for health monitoring and diagnosis, which can prevent the damage to human bodies by those diagnosis instruments with active energy transmission such as X-ray detection and ultrasonic monitoring. A typical implementation of heart sound monitoring sensor is presented. The designed sensor records the heart beat sounds that can be used for real-time and long-term heart rate monitoring.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124167045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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