Failure analysis of output stage due to ESD stress in submicron CMOS technology

ESD failure of an operational amplifier in submicron CMOS technology is analyzed to locate the failure mechanism and re-design the protection structure in this paper. From the experimental results, the specifications related to the output stage with large size devices are degraded or exceed the qualified range. With the deep analysis of internal circuit of the chip, electrical measurement determines the failure mechanism. The protection of power rail is not robust enough for shunting the ESD current under ND and PS modes. RC+BigFET clamp is used to improve the ESD robustness of whole chip to 3500V which is qualified for most applications.