Metrology, Inspection, and Process Control for Microlithography XXXIII最新文献

{"title":"Super-resolution fluorescence nanoscopy opportunities for EUV resist inspection and metrology (Conference Presentation)","authors":"J. Petersen","doi":"10.1117/12.2515260","DOIUrl":"https://doi.org/10.1117/12.2515260","url":null,"abstract":"Stochastic print failures are a serious potential yield limiter for the 5 nm and 3 nm technology node. To attain the detection limits that ensure yield requires inspection of square centimeters of area, which will challenge even the fastest anticipated e-beam tools. Optical techniques help but lack the ability to resolve actual defects. Applying super-resolution fluorescence nanoscopy techniques may provide a solution for both rapid inspection and defect identification capable of inspecting hundreds of wafers per hour. The technique first developed by Stephan Hell in 1994 for the life sciences uses the ability to toggle a molecules fluorescence on and off by activating with actinic light and deactivating via stimulated-depletion. By surrounding activating light with deactivating light, the former’s spot size reduces to nanometers allowing resolutions that far exceed the Abbe limit. In 2014, Professor Hell shared the Nobel Prize in chemistry for this technique, Stimulated-Emission-Depletion, STED nanoscopy. This paper will explain the technique, propose a method in its use for the inspection of EUV resists, and demonstrate proof-of-concept where we imaged with 775 nm deactivation and 640 nm activation morphological structures in a polymer film that are smaller than 5 nm.","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125509887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine learning and hybrid metrology using scatterometry and LE-XRF to detect voids in copper lines","authors":"Kong Dexin, Motoyama Koichi, A. A. D. L. Pena, Huai Huang, B. Mendoza, M. Breton, G. R. Muthinti, H. Shobha, Liying Jiang, Juntao Li, J. Demarest, J. Gaudiello, G. Karve, A. Cepler, M. Sendelbach, Susan Emans, P. Isbester, K. Shah, Shay Wolfing, Avron Ger","doi":"10.1117/12.2515257","DOIUrl":"https://doi.org/10.1117/12.2515257","url":null,"abstract":"Voids in copper lines are a common failure mechanism in the back end of line (BEOL) of integrated circuits manufacturing, affecting chip yield and reliability. As subsequent process nodes continue to shrink metal line dimensions, monitoring and control of these voids gain more and more importance [1]. Currently, there is no quantitative in-line metrology technique that allows voids to be identified and measured. This work aims to develop a new method to do so, by combining scatterometry (also referred to as Optical Critical Dimension or Optical CD) and low-energy x-ray fluorescence (LE-XRF), as well as machine learning techniques. By combining the inputs from these tools in the form of hybrid metrology, as well as with the incorporation of machine learning methods, we create a new metric, referred to as Vxo, to characterize the quantity of void. Additionally, the results are compared with inline electrical test data, as higher amounts of voids were expected to increase the measured resistivity. This was not found to be the case, as the impact of the voids was much less of a factor than variation in the cross-sectional area of the lines.","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"26 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132610917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved sub-surface AFM using photothermal actuation","authors":"Maarten E. v. Reijzen, M. Tamer, M. V. Es, M. Riel, A. Keyvani, H. Sadeghian, M. Lans","doi":"10.1117/12.2515441","DOIUrl":"https://doi.org/10.1117/12.2515441","url":null,"abstract":"In this paper, we present an AFM based subsurface measurement technique that can be used for overlay and critical dimensions (CD) measurements through optically opaque layers. The proposed method uses the surface elasticity map to resolve the presence and geometry of subsurface structures. To improve the imaging performance of the AFM based subsurface measurements, we made use of photothermal excitation of the AFM cantilever together with a frequency modulation scheme. The experimental results show a significant improvement in the quality of the image, which leads to a more accurate and reliable CD and overlay measurement.","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123927051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silicon-based quantum computing: manufacturing and metrology challenges (Conference Presentation)","authors":"R. Silver","doi":"10.1117/12.2517365","DOIUrl":"https://doi.org/10.1117/12.2517365","url":null,"abstract":"Over the last 20 years there has been a steady increase in fundamental physics research and the hardware development needed to realize a quantum computer. However, in the last 5 years we have seen a dramatic increase in the interest from industry, including a variety of major semiconductor and technology leaders such as IBM, Google and Intel. This is the result of both a better understanding of the variety of problems that can be addressed and the impact that will come with quantum computing along with the emergence of a couple of potentially scalable hardware solutions. In a recent interview with a leading manufacturer, an aggressive strategy was laid out to achieve an operational 1000-qubit quantum computer within 5 years that can solve a variety of problems not addressable by conventional computing and the 10-year prospect to achieve a 1 million qubit machine that would “profoundly change society”. \u0000\u0000The major technology leaders view quantum information (QI) as a technology that they must begin to develop and understand today. Augmenting existing technology with QI is desirable, but , there are a variety of technical challenges to making silicon-based QI systems with the needed quantum properties and coherence times. New challenges in atomic precision and individual atom or electron effects that fundamentally affect device performance bring on a variety of new manufacturing and metrology challenges. Measuring electron spin coherence, exchange energies, and qubit fidelity are entirely new measurements for the semiconductor industry. Even the resolution of TEM may be inadequate, as TEM of a nominally 80 nm thick slice of silicon which averages many atoms together in a measurement where only one or two atoms can deeply change device performance, coherence times, or introduce charge offsets. After developing some of the first cold atom and ion trap quantum information demonstrations at NIST, we are now investing significantly in developing the supporting metrology and modeling methods needed to help industry develop and commercialize this new technology.\u0000\u0000In this presentation we will provide an overview of hardware solutions for quantum computing, future metrology needs and challenges to enable manufacturable quantum computers. Although industry leaders are now investing in superconducting qubits and silicon-based qubits, the two leading technologies, this talk will primarily focus on the principles of solid state silicon QI operation, manufacturing metrology solutions, and measurements needed to develop and evaluate viable technological solutions.","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128220785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Massive metrology and failure identification for DRAM applications (Conference Presentation)","authors":"Harm Dillen, D. Oorschot, M. Kooiman, Willem van Mierlo, Ziyang Wang, Kang-san Lee, Jin-Woo Lee, Ruochong Fei, Shu-yu Lai, M. Kea, Inhwan Lee, Hwan Kim, Jung-hyun Kang, Jaehee Hwang, Chang-moon Lim","doi":"10.1117/12.2515487","DOIUrl":"https://doi.org/10.1117/12.2515487","url":null,"abstract":"Introduction and problem statement\u0000Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement.\u0000\u0000Method \u0000We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature. \u0000Fig 1. In line detected anomalies and failure definitions\u0000\u0000As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels.\u0000\u0000Application and outlook\u0000We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3. \u0000Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window.\u0000 \u0000Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131117123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Voltage contrast edge placement estimation for overlay, CD, and local uniformity metrology (Conference Presentation)","authors":"C. Tabery, V. Rutigliani, Hastings Simon, Etienne de Poortere, Luke Wang, P. Leray, G. Schelcher, Yongjun Wang","doi":"10.1117/12.2516613","DOIUrl":"https://doi.org/10.1117/12.2516613","url":null,"abstract":"Voltage contrast (VC) is a long known and well established technique to give combined inline sensitivity to electrically relevant measures of defectivity but also local defect isolation and integrated review SEM making the technique a critical piece of fab wafer inspection. By creation of a special mark design with many local repeats of different CD and overlay set points a voltage contrast response is created which allows the local edge placement error population to be estimated while also capturing a connectivity and isolation yield proxy. This enables high throughput local estimates of overlay, CD, overlay and CD process window and local CD uniformity. \u0000A test mask containing these marks was designed and fabricated at IMEC with metrology done on optical and electron beam inspection systems. Both open and short sensitivity are programmed into the marks and this yield proxy data has inherent value on its own. We propose to integrate these special test marks into some critical layers in modern memory and logic process flows with a design which can be added to scribe lines or empty regions/in die test structures in logic or empty regions of the memory periphery. Significant design and process knowledge is required to design a mark which can integrate with the process and give good EPE sensitivity. \u0000Initial mark designs have been targeted at single damascene copper on tungsten with VC inspection after copper polish. Initial results show a high baseline yield loss but also show clear and intuitive CD and Overlay process window quantification from the VC EPE marks. Marks as large as ~100,000 um2 and as small at 250um2 have been designed and enable overlay, CD, LCDU and with yield sensitivity to ~1 part per million for the larger marks and ~1% for the smallest marks. With the expected productivity of the ebeam inspection system we should be able thousands of marks per wafer or field to support diverse overlay, CD and control use models and process fingerprint mapping.","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121641256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On device EPE: minimizing overlay, pattern placement, and pitch-walk, in presence of EUV stochastics and etch variations (Conference Presentation)","authors":"O. Adan, Kevin Houchens","doi":"10.1117/12.2517284","DOIUrl":"https://doi.org/10.1117/12.2517284","url":null,"abstract":"EUV lithography and multi patterning introduce variability often referred to as EUV and Etch stochastics. These consume a large part of the EPE (Edge Placement Error) budget. To bring EPE to the necessary specifications, the industry needs to minimize the key EPE contributors of CD, Overlay, pattern placement, pitch-walk, and LER. The challenge is that these attributes are being gauged by different metrology technologies, thus just matching these different metrology techniques might consume the entire EPE budget. Hence, the industry has sought solutions presented in this work that are capable of measuring the above attributes of EPE from a single image. The study presented will then investigate weather measuring all of EPE on a scribe like target introduces a pitch dependent bias that could be rid of - if all of EPE was measured on device. The paper will show data from thousands of EUV vias over multi-patterned interconnects of a real device. \u0000Once established that measuring on device is not prone to pitch dependent bias. The work will compare measuring and correcting EPE at ADI - after develop inspection, to reduce the time to accuracy compared to known methods of measuring accuracy, only at AEI, after etch. An attempt is made to investigate weather after etch accuracy methods used today insert a litho to etch metrology driven bias.\u0000After walking the audience through an EPE metrology budget minimization flow based on real images and data, the paper will look for further opportunities to minimize EPE at the source, such as self-aligned processes, beyond litho, specifically discussing spacer uniformity, and etch slant control versus overlay.","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"40 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131851915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D-SEM challenges: How can we profile in-die 3D geometry of the integrated circuits? (Conference Presentation)","authors":"Makoto Suzuki, Ayumi Doi","doi":"10.1117/12.2514944","DOIUrl":"https://doi.org/10.1117/12.2514944","url":null,"abstract":"Device miniaturization and complication is now stimulating the strong needs for the three dimensional (3D) geometry measurement of the structure. Now in the single-nanometer nodes, the CDs need to be known at multiple pattern heights especially in after-etch inspection. This means SEM measurements is expected to provide 3D contours. Unfortunately, CD-SEM is basically top-down imaging tool, therefore the acquired micrograph is the 2D projection of the device structure. Meanwhile, optical CD (OCD) works well to deduce the 3D geometrical parameters. Due to the spot size limitation, however, it is hard to obtain the local variation of the structure, or hard to access in-die metrology data. While TEM or slice and view by FIB-SEM is a reliable option to see the local 3D structure, they are destructive and low in statistics due to the long turn-around time. Therefore the challenge is, how to obtain in-die 3D geometrical information in non-destructive way.\u0000The purpose of the present work is to extend CD-SEM capability to extract 3D geometry. The most intuitive approach is the direct imaging, where the structure can be extracted directly from the acquired image. The direct imaging includes, beam tilt SEM and topography detector. While the beam tilt is an intuitive method, at larger tilt over 10 degrees the image blur is unavoidable and the precise metrology application is difficult unless the small tilt angle is enough to see the side wall structure like high-aspect-ratio (HAR) structure over several microns in depth. Topography detector is another well-known approach, and works well for the isolated target like particles or pattern defects. In the smallest spacing, however, characteristic shadow is not created, and the topography extraction is basically difficult. By these reasons, we especially have a strong interest in indirect methods described below.\u0000Indirect approach includes model-based geometry matching and hybrid metrology with other reference measurements. In these approaches, it is required to find the characteristic SEM waveform or signal intensity (gray-level) which are sensitive to the target geometry. The sensitivity of the response can be estimated by the simulation models, or the comparison with other 3D measurements tools like OCD or AFM. The concept is the generalization of the model-based library (MBL), where the SEM waveform is compared with pre-calculated library of the waveforms. In our approach, calibration could be done by using simulation data or real 3D profiling data. Another generalization is that a SEM operation condition is also altered to enhance the sensitivity of all the geometrical parameter. For example, by sweeping the beam voltage, the multiple waveforms are obtained and the low voltage data has a sensitivity in the pattern top geometry, and the higher voltage data in the pattern bottom. Similar parameter sweep can be applied to energy-filter voltages or focus heights. It is expected that this sort of the generalizati","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"402 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122099966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Variable-wavelength tabletop-scale EUV ptychographic complex imaging reflectometry for 3D composition determination (Conference Presentation)","authors":"M. Tanksalvala, Christina L. Porter, Yuka Esashi, Galen P. Miley, Robert M. Karl, Peter C Johnsen, N. Jenkins, C. Bevis, Bin Wang, J. Thurston, Xiaoshi Zhang, S. Cousin, D. Adams, M. Gerrity, H. Kapteyn, M. Murnane","doi":"10.1117/12.2516827","DOIUrl":"https://doi.org/10.1117/12.2516827","url":null,"abstract":"","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133168455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LER and LWR measurements used for monitoring wiggling and stochastic-failure (Conference Presentation)","authors":"H. Kawada, Yasushi Ebizuka, T. Sutani, T. Kawasaki","doi":"10.1117/12.2515803","DOIUrl":"https://doi.org/10.1117/12.2515803","url":null,"abstract":"We have previously demonstrated our method to obtain unbias dense line’s LER (Line Edge Roughness) processed by EUV (Extreme Ultra-Violet) lithography. No special edge-detection, simulation modeling, beam-scan, nor image processing is required, except optimization of beam-dose parameters. For instance, threshold method that is a conventional edge-detection is used on SEM (Scanning Electron Microscopy) image taken by a conventional beam-scanning with a conventionally used beam-conditions. However, especially for EUV-lithographed features we must determine carefully landing voltage and beam-dose that cause artificial reduction of LER and LWR (Line Width Roughness) due to shrink of photo resist materials. \u0000Note that we made edge-detection interval at every 5 nm, that is as small as probe-beam diameter. For instance, we set the vertical magnification, the pixel-density, and the sum-line-per-point parameter at 52.7k, 1024, and 2, respectively. Although we can make the interval as small as sub-nanometer, it is not reliable to measure the sub-nanometer object that is only one-tenth of the probe-beam diameter.\u0000Then, we verified accuracy of our unbiased LWR by using two independent experimental methods: TEM and FIB-SEM. We obtained spectra of PSD (Power Spectrum Density) from the TEM, the FIB-SEM and our unbiassing CDSEM-method. We found the three PSDs agreed very well to each others. This result strongly implies that three independent methods measured an identical PSD, of true LWR. By our unbiassing CDSEM-method we can measure the true LWR which is calculated from the true PSD. \u0000In this work, by using the similar experimental-methods we verify accuracy of our wiggling measurement. Wiggling is a hot issue in production yield of post dry-etch process. Especially about 20 nm or less in the line-width, wiggling starts appearing due to decreased elastic-stiffness of the line feature. \u0000A reason why we study the accuracy of LER, LWR, and wiggling is inline monitor of stochastic failures. As they increase significantly in EUV lithography process, production yield may not be promising. Bisshop et al. [1] investigated pitch and/or space-width correlate to incidence of stochastic-failures, such as breaking-line and bridging-line, down to ppm (parts per million). However, the incidence of the stochastic failures should be reduced less to ppb (parts per billion) or ppt (parts per trillion) which is as small as tolerable particle contamination on a wafer. \u0000This implies significance of accurate LWR and/or wiggling monitor because in narrow line or space a-few-nanometer-LWR narrows locally them the more and causes the more stochastic failures. \u0000In this work, in order to control ppb-stochastic failures we figure out a correlation between LWR and the failures’ incidence. We need to measure billions of features, that requires too long measurement time for practical process-monitor. To shorten the measurement time we test an effective method to estimate such very few number","PeriodicalId":331248,"journal":{"name":"Metrology, Inspection, and Process Control for Microlithography XXXIII","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130650237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}