2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition最新文献

{"title":"Newly developed high reliability palladium coated Cu wire for automotive application","authors":"M. Eto, T. Haibara, R. Oishi, Takashi Yamada, T. Uno, T. Oyamada","doi":"10.23919/EMPC.2017.8346848","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346848","url":null,"abstract":"In the past several years, Au bonding wire has been replaced with Cu wire in the field of LSI devices. In particular, Pd coated copper (PCC) and Au-Pd coated copper (APC) wire are the majority of the market share. Recently, a shift from Au wire to Cu wire is also expected for automotive devices. In order to apply Cu wire to automotive devices, high bond reliability is required under harsh environment. Especially, high temperature is a major concern to design and manage long term reliability. A new type of APC (new-APC) wire was developed to have better thermal reliability than bare Cu and conventional APC wire. New-APC wire has higher concentration of added element than APC wire. Furthermore, the new-APC wire has good bond properties similar to APC wire.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"50 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132606084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Image approximation using B-spline surfaces","authors":"Z. Suszyński, R. Świta","doi":"10.23919/EMPC.2017.8346882","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346882","url":null,"abstract":"This article presents a method of filtering thermal images by means of approximation using cubic B-Spline patch surfaces. Approximation uses chord-length parameterization with non-uniform distribution of knots, depending on the change rate of pixel values in rows and columns of the image. Advantages of approximation with such parameterization are compared with popular uniform parameterization. Presented method is very versatile and can be used for example in 3D surface topography of objects tested with stereoscopic microscopes, in resolution change of arbitrary images or modeling processes depending on two parameters. Filtering results are presented using plugin for the Soft4Image program, which was designed to unify different digital signal processing algorithms.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132338282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability of copper-based interconnections for power devices","authors":"M. Guziewicz, K. Pągowska, A. Laszcz, M. Myśliwiec","doi":"10.23919/EMPC.2017.8346926","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346926","url":null,"abstract":"A new type of interconnections in power devices could be based on copper due to higher electrical and thermal conductivity, and significantly lower material price than for Au. This work presents fabrication technology of Cu-based interconnections for high power transistors and results of interconnections reliability. Magnetron co-sputtering deposition method was applied to create Cu alloys with Ru, Hf, Nb, NbN additives, as well as adhesion layers of Ti, NbN or NbTiN. Interconnection reliability was evaluated on test structures, where Cu lines were protected by thin metallic or dielectric cap against oxidation in air. Crystal structure of the Cu film is stabilized by small amount of Nb or NbN additive. Formed interconnections ensure resistivity below 5 μΩcm. Resistance of the Cu interconnection is stable after ageing in air at 250oC and at current stress of 5 MA/cm2 for few hundred hours, while an insignificant increase in resistance is observed after 200 h ageing at 300oC and current stress of 2 MA/cm2.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115086487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A new method for prediction of corrosion processes in Aluminum housing materials for electronic components","authors":"S. Klengel, T. Stephan, Bolko Mühs-Portius","doi":"10.23919/EMPC.2017.8346858","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346858","url":null,"abstract":"We developed a method based on potentiostatic measurements which allows corrosion sensitivity analyzes of coated Aluminum housings in a very short time. Using a NaCl electrolyte combined with electrical potential accelerates the corrosion reaction and initiates typical application related corrosion processes. In this paper we will present and discuss our method for corrosion testing in correlation to the standard salt spray test. Furthermore high resolution microstructural analyzes are giving evidence for the running corrosion process. We will show microstructural results by Scanning Electron Microscopy (SEM) and element analyzes (EDS) for samples potentiostatic tested. Finally the corrosion processes induced will be compared and discussed.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124672871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A delamination study on metallization stacks of power semiconductors","authors":"T. Walter, G. Khatibi","doi":"10.23919/EMPC.2017.8346902","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346902","url":null,"abstract":"The requirements on the interfacial strength of metallization stacks in modern power semiconductor devices are becoming more and more demanding. Delamination is a common failure mode found in such microelectronic components. Residual stresses, originating during deposition commonly occur in these metallization film stacks. It has been demonstrated that these residual stresses can significantly change the driving force for interfacial delamination. The four-point bending (4PB) test is an appropriate method to quantitatively measure the delamination resistance and energy release rate. In this study the influence of Cu metallization thickness and residual stresses on the adhesion strength of SiOx/SiNx/TiW/Cu film stacks on Silicon were investigated. In addition to detailed microstructural and chemical analysis of the film stacks and its interfaces, we used X-ray diffraction (XRD) residual stress measurements as well as wafer bow methods to estimate the stress in the Cu films and the film stack respectively. Static 4PB technique was used in order to determine the interfacial adhesion properties of the samples. In addition Finite Element Analysis was performed to verify analytical calculations. Delamination occurred always in the interface between Si and the amorphous SiOx layer. This can be explained by the loading conditions imposed by the 4PB set-up and the selected sample geometry.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127551531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of heating direction on BGA solder balls structure","authors":"A. Otáhal, J. Somer, I. Szendiuch","doi":"10.23919/EMPC.2017.8346878","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346878","url":null,"abstract":"The soldering of BGA packages is well known process. Despite the increasing complexity of PCBs and diversity of BGA package footprints, further optimization and improvement of soldering is required. In this paper, the influence of heat flow direction during reflow soldering on the structure of ball joint was described. The SAC305 solder alloy was used for ball joint investigation under the no-clean solder flux condition. Tested samples were made from FR4 material with ENIG as a surface finish. The heating was generated by infrared heaters placed on the top, bottom and both sides of the sample. The substantial part of this work was focused on the characterization the solder joint structure with the respect to the intermetallic compounds formation. SEM and optical microscope images of cross-sectioned solder joints were used to characterize the quality of the boundary formation. Shear test method was used to evaluate the impact of intermetallic layer and inner solder joint structure on the mechanical properties of joints. This research helps to determine the influence of the direction of heat flux, i.e. direction of heating of the infrared heater used in the reflow soldering, for the formation of the solder ball joint on BGA package (primarily for rework).","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121642235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pulse stability of low ohmic thick-film resistors","authors":"A. Dąbrowski, Jakub Czarachowicz, A. Dziedzic","doi":"10.23919/EMPC.2017.8346887","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346887","url":null,"abstract":"Durability of low ohmic thick-film resistors on pulse load with micro-and milisecond duration are described in this paper. Standard thick-film resistive compositions with sheet resistance of 10 Ohms/sq (4311 and QS871 — DuPont; R400-10A — Heraus) and 3 Ohms/sq (QS870 — DuPont) were tested. Test resistors with resistance of 3 Ω were prepared on alumina substrates. Resistance changes were measured after 50 pulses at each voltage. Then the voltage was increased and the series of pulses were repeated until the resistance change exceeded 0.5%. The resistors made of 4311 paste exhibited the highest durability for long (20 ms) pulses, when the thermal interface between substrate and heatsink was filled by thermally conductive grease. The relative resistance change of +0.5% was observed at about 19 W/mm2 and about 18 W/mm2 for the samples with and without the overglaze, respectively. Short (microsecond) pulses had the least influence on QS871 paste, for which the resistance change of +0.5% was observed at electric field intensity of about 90 ± 10 V/mm. For 4311 paste the parameter reached maximum 50 ± 10 V/mm, whereas for R400-10 as well as QS870 pastes the value didn't exceed 40 ± 10 V/mm.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124075585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modelling power LEDs in the COB case with thermal phenomena taken into account","authors":"K. Górecki, Przemysław Ptak","doi":"10.23919/EMPC.2017.8346884","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346884","url":null,"abstract":"The paper refers to modelling power light emitting diodes (LEDs) in the SPICE software with thermal phenomena taken into account. The electro-thermo-optical model of such diodes contained in the common chip on the board (COB) case and the results of experimental verification of the correctness of this model are presented. A good agreement between the results of calculations and measurements was obtained, for operation of the considered diode both in static and dynamic conditions.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122091020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Depositing of conductive silver nanoparticles layer on cellulose fibers","authors":"Olga Rac-Rumijowska, M. Fiedot-Toboła, P. Suchorska-Woźniak, I. Karbownik, A. Stafiniak, H. Teterycz","doi":"10.23919/EMPC.2017.8346908","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346908","url":null,"abstract":"In this paper a method for forming a conductive layer of silver on cellulose fibers was presented. The metallic layer was deposited from a solution containing silver nanoparticles (AgNPs) of 20–30 nm in diameter. Two types of cellulose fibers were used as a substrates: undoped fibers and nanocomposite cellulose fibers doped with silver nanoparticles. The obtained layer had a good adhesion to the substrate. The high impact on the layer properties had AgNPs in fibers volume, which were the crystallization centers. The electrical conductivity measurements were performed by the impedance spectroscopy method.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129288864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine pitch high bandwidth flip chip package-on-package development","authors":"M. Hsieh, Stanley Lin, I. Hsu, Chi-Yuan Chen, NamJu Cho","doi":"10.23919/EMPC.2017.8346847","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346847","url":null,"abstract":"As the demands of higher performance, higher bandwidth, lower power consumption as well as multiple functions increases in mobile applications, the mobile phone has evolved from a simple communication device to a complicated and highly integrated system with multiple functions and heterogeneous devices. Due to the fast growth in emerging markets for mobile applications, packaging technology has become more challenging than ever before, driving advanced Silicon (Si) nodes, finer bump pitch as well as finer line width and spacing substrate manufacturing capabilities to satisfy the increasing requirements in mobile devices. Flip chip chip scale package (fcCSP) is viewed as an attractive solution when higher input/output (I/O) counts in a package are needed. In order to enhance the performance, reduce the power consumption and increase transition rates, three-dimensional (3D) package-on-package solution with flip chip interconnect (fcPoP) has been widely utilized to successfully achieve these goals. With the ability to stack a logic processor and low power double data rate (LPDDR) memory device in a single package, the utilization of fcPoP is becoming a preferred solution in the mobile market segment for a better power and performance balance. However, as more and more functions are designed in a chip to target the high-end mobile market, the die is becoming larger and larger. With the larger die size, it is challenging for the regular fcPoP structure to support high bandwidth top memory I/O counts in a limited package size. In order to solve the constraints of larger die and/or package size limitations, top memory with wide I/O counts as well as customized mobile memory applications, high bandwidth fcPoP technology is proposed as an strong solution. This paper reports the development of a fine pitch high bandwidth fcPoP. The top interposer substrate with copper (Cu) post interconnections peripherally is connected to bottom package. The top interposer substrate can be designed in a different top and bottom pitch to connect top mobile memory and bottom packages, respectively. With this structure, die size limitations can be overcome by using finer interconnection pitch, providing the flexibility to allow any memory interface pitch application. In addition, through this developed result, not only the package warpage/coplanarity control and reliability characterization are illustrated, it also demonstrated this enabling technology of high bandwidth fcPoP as a highly integrated, miniaturized and low profile 3D packaging solution.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132700174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}