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1995 Symposium on VLSI Technology. Digest of Technical Papers最新文献

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Novel oxynitridation technology for highly reliable thin dielectrics 用于高可靠性薄电介质的新型氧化氮化技术
1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1995-06-06 DOI: 10.1109/VLSIT.1995.520880
M. Joo, Seok-Hee Lee, Seok-Kiu Lee, Byungsu Cho, Jong-Choul Kim, S. Choi
{"title":"Novel oxynitridation technology for highly reliable thin dielectrics","authors":"M. Joo, Seok-Hee Lee, Seok-Kiu Lee, Byungsu Cho, Jong-Choul Kim, S. Choi","doi":"10.1109/VLSIT.1995.520880","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520880","url":null,"abstract":"A new oxynitridation technology is introduced. The oxynitride gate dielectric was grown in light wet ambient by diluting NH/sub 3/ gas in N/sub 2/O using a low pressure furnace. The oxide growth rate could be enhanced by this technique. The electrical properties of the oxide were improved by hardening of both SiO2 bulk and Si/SiO2 interface with in-situ post N/sub 2/O annealing. This technology is very promising for gate dielectrics in next generation DRAM and Flash EEPROM devices.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117203439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new method to monitor gate-oxide reliability degradation 一种监测栅极氧化物可靠性退化的新方法
1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1995-06-06 DOI: 10.1109/VLSIT.1995.520869
K.P. Cheung
{"title":"A new method to monitor gate-oxide reliability degradation","authors":"K.P. Cheung","doi":"10.1109/VLSIT.1995.520869","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520869","url":null,"abstract":"Recently, a new method which uses the initial electron trapping rate (IETR) of the gate-oxide to detect plasma damage was introduced. In this paper, the transistor hot-carrier life-time (HCLT) degradation due to plasma damage is shown to be related to the IETR, and thus establishes a new way to monitor gate-oxide reliability. The IETR is directly proportional to the pre-existing electron-trap density. Thus hot-carrier degradation in plasma damaged gate-oxide is by electron trapping instead of by interface-state generation normally expected for n-channel transistors. In addition, post Fowler-Norhein (FN) stress transistor parameter variation due to plasma damage is also shown to be linear to the IETR. A relationship between the hot-carrier stress method and the FN stress method for plasma induced latent damage measurement is thus established.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122675537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Highly porous interlayer dielectric for interconnect capacitance reduction 用于降低互连电容的高多孔层间介质
1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1995-06-06 DOI: 10.1109/VLSIT.1995.520858
S. Jeng, K. Taylor, T. Seha, M. Chang, J. Fattaruso, R.H. Havemann
{"title":"Highly porous interlayer dielectric for interconnect capacitance reduction","authors":"S. Jeng, K. Taylor, T. Seha, M. Chang, J. Fattaruso, R.H. Havemann","doi":"10.1109/VLSIT.1995.520858","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520858","url":null,"abstract":"Hydrogen silsesquioxane (HSQ) is a low density material for intra-metal gapfill, that offers low permittivity for interconnect capacitance reduction. Films with k as low as /spl sim/2.2 preferentially form between tightly-spaced metal leads when cured at low temperature (<400/spl deg/C), and interlayer dielectric properties are stable from 1 MHz to 1 GHz. HSQ simplifies the process integration of low-k materials for high performance interconnect applications by using standard semiconductor spin-on production techniques. Use of porous HSQ as a gapfill dielectric dramatically reduces the capacitive coupling between metal leads, resulting in higher interconnect performance.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"17 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123520963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
High quality ultra-thin (4 nm) gate oxide by UV/O/sub 3/ surface pre-treatment of native oxide 采用UV/O/sub - 3/表面预处理的高品质超薄(4nm)栅极氧化物
1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1995-06-06 DOI: 10.1109/VLSIT.1995.520882
S. Ohkubo, Y. Tamura, R. Sugino, T. Nakanishi, Y. Sugita, N. Awaji, K. Takasaki
{"title":"High quality ultra-thin (4 nm) gate oxide by UV/O/sub 3/ surface pre-treatment of native oxide","authors":"S. Ohkubo, Y. Tamura, R. Sugino, T. Nakanishi, Y. Sugita, N. Awaji, K. Takasaki","doi":"10.1109/VLSIT.1995.520882","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520882","url":null,"abstract":"A significant improvement in ultra-thin (4 nm) gate oxide quality has been carried out using UV/O/sub 3/ pre-treatment of native oxide before thermal oxidation. UV/O/sub 3/ pre-treatment makes native oxide dense and close-packed without leaving any residue species. Ultra-thin gate oxide formed by UV/O/sub 3/ pre-treatment and O/sub 3/ oxidation has been found to have excellent behavior, low leakage current, low surface state density, and superior dielectric breakdown characteristics. UV/O/sub 3/ pre-treatment looks promising for using in ultra-thin gate oxidation necessary for 0.1 /spl mu/m ULSI fabrication.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127987789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 62.8 GHz fmax LP-CVD epitaxially grown silicon base bipolar transistor with extremely high early voltage of 85.7 V 一种62.8 GHz fmax LP-CVD外延生长硅基双极晶体管，早期电压高达85.7 V
1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1995-06-06 DOI: 10.1109/VLSIT.1995.520892
C. Yoshino, K. Inou, S. Matsuda, H. Nakajima, Y. Tsuboi, H. Naruse, H. Sugaya, Y. Katsumata, H. Iwai
{"title":"A 62.8 GHz fmax LP-CVD epitaxially grown silicon base bipolar transistor with extremely high early voltage of 85.7 V","authors":"C. Yoshino, K. Inou, S. Matsuda, H. Nakajima, Y. Tsuboi, H. Naruse, H. Sugaya, Y. Katsumata, H. Iwai","doi":"10.1109/VLSIT.1995.520892","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520892","url":null,"abstract":"Optimization of fmax and VA values was investigated by changing Wcpi and NB Values of low temperature LP-CVD epitaxial base. It was found that there are optimum conditions which can realize concurrent extremely high fmax value-more than 50 GHz-and extremely high Vn value-more than 50V-in the case of silicon epitaxial base bipolar transistors with silicided emitter and base electrodes. Relatively flat profile of boron in the epitaxial base region can realize high Vn value with high fmax. NiSi emitter and base electrodes technology can further increase the fmax value. The highest fmax value of 62.86 Hz at a collector current of 1.7 mA was achieved. High BVCBO of 4.7 V, high VA of 85.7 V and low p/sub BI/ value of 8.5 k/spl Omega//sq were also realized at the same time.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128403761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
New CoSi/sub 2/ SALICIDE technology for 0.1 /spl mu/m processes and below 新的CoSi/sub 2/ SALICIDE技术，适用于0.1 /spl mu/m及以下工艺
1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1995-06-06 DOI: 10.1109/VLSIT.1995.520838
Q.F. Wang, K. Maex, S. Kubicek, R. Jonckheere, B. Kerkwijk, R. Verbeeck, S. Biesemans, K. De Meyer
{"title":"New CoSi/sub 2/ SALICIDE technology for 0.1 /spl mu/m processes and below","authors":"Q.F. Wang, K. Maex, S. Kubicek, R. Jonckheere, B. Kerkwijk, R. Verbeeck, S. Biesemans, K. De Meyer","doi":"10.1109/VLSIT.1995.520838","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520838","url":null,"abstract":"A new CoSi/sub 2/ salicide technology with thin Ti capping layer has been developed to improve the formation and thermal stability of sub-0.1 /spl mu/m CoSi/sub 2//Poly stacks. Previously both Co/Ti and conventional processes have been used successfully to produce 0.1 /spl mu/m lines. However, the former technique has a wider process window to obtain uniform silicide films reproducibly.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128712784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Highly reliable 0.15 /spl mu/m MOSFETs with Surface Proximity Gettering (SPG) and nitrided oxide spacer using nitrogen implantation 高可靠性的0.15 /spl mu/m mosfet，采用表面接近捕集(SPG)和氮化氧化物间隔
1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1995-06-06 DOI: 10.1109/VLSIT.1995.520839
T. Kuroi, S. Shimizu, A. Furukawa, S. Komori, Y. Kawasaki, S. Kusunoki, Y. Okumura, N. Inuishi, N. Tsubouchi, K. Horie
{"title":"Highly reliable 0.15 /spl mu/m MOSFETs with Surface Proximity Gettering (SPG) and nitrided oxide spacer using nitrogen implantation","authors":"T. Kuroi, S. Shimizu, A. Furukawa, S. Komori, Y. Kawasaki, S. Kusunoki, Y. Okumura, N. Inuishi, N. Tsubouchi, K. Horie","doi":"10.1109/VLSIT.1995.520839","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520839","url":null,"abstract":"An advanced nitrogen implantation technique is proposed. The new technique can suppress remarkably the hot carrier degradation. Since the generation of interface states can be reduced by the incorporation of nitrogen at the interface between a substrate and SiO/sub 2/ spacers. Moreover, the ultra shallow junction without the increase in leakage current can be formed by nitrogen implantation into the source/drain. Since the secondary defects induced by nitrogen implantation can act as a surface proximity gettering (SPG) site.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124987788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
1995 Symposium on VLSI Technology. Digest of Technical Papers 1995超大规模集成电路技术研讨会。科技论文摘要
1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/VLSIT.1995.520831
応用物理学会
{"title":"1995 Symposium on VLSI Technology. Digest of Technical Papers","authors":"応用物理学会","doi":"10.1109/VLSIT.1995.520831","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520831","url":null,"abstract":"","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117029750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
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