2007 8th International Conference on Electronic Packaging Technology最新文献

{"title":"Chip Package Interaction in Ultra Low-k/Copper Interconnect Technology","authors":"X. Liu, T. Shaw, E. Liniger, M. Lane, G. Bonilla, J. Doyle, B. Herbst, D. Questad","doi":"10.1109/ICEPT.2007.4441569","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441569","url":null,"abstract":"In this paper a methodology based on fracture mechanics has been used to investigate the chip package interaction of ultra low-k/copper interconnect. When a wafer is diced into chips, defects can be generated at the edge of the chips. Under the thermal stress from the package the defects can propagate into the dielectric and cause the chip failure.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133721320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimal Design of SnAgCu-CNT Solder Lap-shear Specimen under Thermal Cycles with FEM","authors":"Yongdian Han, H. Jing, Lianyong Xu, Jun Wei","doi":"10.1109/ICEPT.2007.4441461","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441461","url":null,"abstract":"In this study, multi-walled carbon nanotubes were successfully incorporated into Sn95.5Ag3.8Cu0.7 solder to synthesize novel lead-free composite solders. The paper presents a numerical approach to track the shear stress and creep strain behaviors at the solder joint in lap-shear specimen subject to thermal process. Some notches with different sizes and shapes are designed on the substrate next to the solder. In the investigation, using FEM, the distribution of shear stress and creep strain is simulated and compared under the same conditions but different notch designs. The analytical results show that the distribution of shear stress and creep strain embodies obvious periodicity. The shear stress varies nearly in-phase with the temperature while creep strain does out of phase with temperature. The triangular and round notches are helpful to uniform the range of shear strain. In triangular and round notch designs, notch size does little to affect the distribution of creep strain.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131801062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automatic Focus Algorithm for IC Wafer Image Sampling by Adaptive Lifting Scheme Denoising","authors":"Deng Yaohua, L. Guixiong, Wu Liming, Zhang Yingmin, W. Guitang","doi":"10.1109/ICEPT.2007.4441522","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441522","url":null,"abstract":"High SNR (signal to noise ratio) image is deeply needed in the precise analysis of IC wafer micro-image; current denoising algorithms cant reach the analytic precision in some level. In tins paper, one image denoising algorithms is putted forward based on adaptive lifting scheme, the construction of Haar wavelet and CDF (2,2) is given, the signal is decomposed by wavelet base Haar or wavelet base CDF (2,2) adaptively along four directions (horizon, verticality, 45 degree and 135 degree) in the step of predicting, the wavelet coefficients are calculated separately at each direction, all the thresholds are gained using wavelet soft-thresholding principle, the optimal thresholds minimize the error of the result as compared to these the signal is decomposed along horizon and verticality. Finally the definition of the image is appraised with gray gradient judging function, the experimental data shows that the focus error is no more 4 um, the display definition of the image is improved.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132120323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Preparation of Microcones Array Material for Microelectronic Package","authors":"Kailin Liu, Huiqin Ling, Ming Li, D. Mao","doi":"10.1109/ICEPT.2007.4441467","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441467","url":null,"abstract":"Microcones arrays of cobalt were prepared by electrodeposition with special crystallization conditioning agent. The influence of electrodepositing conditions and form factor effect on the morphology of microcones array is reported. X-ray diffraction result indicated that the Co arrays growing with (110) preferred orientation. The Co array had an obvious magnetic anisotropy. The coercive and saturation field perpendicular and parallel to the surface of Co were FE-SEM, XRD and VSM, respectively.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123092429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microstructure of Ag-Sn Bonding for MEMS Packaging","authors":"Xiaogang Li, Jian Cai, Y. Sohn, Qian Wang, Woon-Bae Kim, Shuidi Wang","doi":"10.1109/ICEPT.2007.4441377","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441377","url":null,"abstract":"Different metallization systems and bonding designs of Ag-Sn bonding were investigated to achieve good bonding. The bonding strength was evaluated by shear force. The microstructure of bonding interface was inspected by scanning electronic microscopy and ED AX. Shear force test was performed for as-bonded dice. The test results indicate differences among different metallization systems. The bonding pair with Ti/Au as the UBM has a quite low shear strength because of the bad adhesion on the silicon substrate. The bonding pair of Ti/Ni/Sn/Au and Ti/Ni/Au/Ag obviously has higher shear strength than that of Ti/Ni/Sn/Au and Ti/Ni/Au/Ag/Au. The former is 55.17 MPa on average while the later is 36.05 MPa. The shear strength of the pair of Ti/Ni/Sn/Au and Ti/Ni/Au/Ag is similar to that of Ti/Ni/Sn/Au and Ti/Ag which has the shear strength of 55.32 MPa on average. The Ni and Au in the Ag-Sn bonding system have significant effect on the microstructure of the bonding interface. The diffusion of Au into Sn is quicker than both Ag and Ni. The diffusion between Au and Sn would induce the obstacle of the inter-diffusion between Sn and Ag. Ni will also diffuse quickly into Sn and form Ni3Sn4. The existence of Ni in Sn will also influence the diffusion of Ag into Sn and make the bad wettability during bonding. After several metallization systems have been investigated, finally a uniform bonding layer has been achieved by excluding Ni and Au in the bonding system. The bonding interface is Ag3Sn layer dispersed with some pure Ag.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134041038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Performance Molding FCBGA Packaging Development","authors":"Ho-Yi Tsai, J. Huang, S. Chiu, C. Hsiao","doi":"10.1109/ICEPT.2007.4441483","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441483","url":null,"abstract":"In this paper, new molding underfill structure is proposed. It shows many advantages, including a) good package coplanarity b) lower bump stress c) lower 2nd level ball stress d) provide no limitation component design. Mold compound can hold big die and substrate together to keep good package coplanarity and give a uniform interface condition within big die area. Droping in heat spreader design gives the largest flexibility of die size and passive component size/number. Mold compound properties can be tailored to meet solder bump and low-K requirements. In addition, mold compound properties have high potential to meet Pb-free solder bump and low-K requirements. A high reliability, high thermal performance, and low package stress molding flip chip ball grid arrays structure is named terminator FCBGA. It has many benefits, like better coplanarity. high through put (multi pes per shut in molding process), low bump stress, and high thermal performance. In conventional flip chip structure, underfill dispenses and cure processes are a bottleneck due to low through put (dispensing unit by unit). For the high performance demand (high pin counts are necessary), large package/die size with more integrated functions needs to meet reliability criteria. Low k dielectric material, lead free bump especially and the package coplanarity are also challenges for package development. Besides, thermal performance is also a key concern with high power device. Low-k has become a hot topic as most 90nm devices and all 65nm devices utilize low-k dielectric. But low-k materials have very low mechanical strength compared to the traditional dielectric films due to their porous nature, which results in lower cohesive strength. Additionally, the tight bump pitch and low standoff height of future packages reduce the flow performance of conventional liquid capillary underfill (CUF) that results in low productivity (low unit per hour (UPH)) and low throughput. From simulation and reliability data, this new structure can provide strong bump protection and reach high reliability performance and can be applied for low-K chip and all kind of bump composition such as tin-lead, high lead, and lead free.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133256273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Die Bonding Process Research for SOI Membrane Pressure Sensor","authors":"R. Guan","doi":"10.1109/ICEPT.2007.4441396","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441396","url":null,"abstract":"Silicon pressure sensors which are based on piezoresistive effect are in use for many fields, because of their high performance and productivity. However, when work environment temperature is over 125degC, silicon piezoresistive pressure sensors have not been used because of worse temperature performance. SOI piezoresistor pressure chip has better temperature performance than silicon pressure sensor and has evidence advantage in aspects of resisting temperature, radiation and corrosion. The SOI pressure sensor of beam-diaphragm packaging structure which can resist high temperature of 250degC has been developed and its packaging process is analyzed in the paper.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132589049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Independent Intellectual Property Product LIP Package of Huatian Technology","authors":"Xiao-Feng Guo","doi":"10.1109/ICEPT.2007.4441573","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441573","url":null,"abstract":"This work reviews the LIP packaging application in the company of Huatian Technology.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116921859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electromigration Time to Failure Simulation for Solder Bumps of a Chip Scale Package","authors":"Shinan Wang, L. Liang, Yuanxiang Zhang, Y. Liu, S. Irving, T. Luk","doi":"10.1109/ICEPT.2007.4441511","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441511","url":null,"abstract":"This paper studies the numerical simulation method for electromigration in the solder joint of a chip scale package. The three dimensional electromigration finite element model for solder joint reliability is developed. Numerical experiments are carried out to obtain the electrical, thermal and stress fields with the migration failure under high current density loads. The indirect coupled analysis that includes electrical, thermal and stress fields are investigated and discussed. The viscoplastic and constitutive material model with both SnPb and SnAgCu solder materials is considered in the paper. The sub-model technique is studied with indirect coupled multiple fields. The impacts of geometry parameters, which include ball shape, trace width and UBM diameter for void formation and electromigration time to failure (TTF) are finally investigated.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123271898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Local Melting and Formation Steps of Solder Bumps via Induction Heating Reflow","authors":"Hongbo Xu, Mingyu Li, Gang Cheng, Jongmyung Kim, Daewon Kim","doi":"10.1109/ICEPT.2007.4441385","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441385","url":null,"abstract":"This work focuses on the nonuniform melting process and its theoretical explanation. After induction heating for 0.8 s, 1.0 s, 1.4 s and 2.0 s, different welding state can be obtained, which gives a proof of the melting process. The experiment results demonstrate that the skin effect of induction heating forms the great temperature gradient in the solder bump. The computation results give a theoretical support of the local melting phenomena. The surface melting of solder ball can affect the height and shape of the solder bumps, which is an important factor of the thermal reliability for BGA.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123404642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}