{"title":"High Performance Molding FCBGA Packaging Development","authors":"Ho-Yi Tsai, J. Huang, S. Chiu, C. Hsiao","doi":"10.1109/ICEPT.2007.4441483","DOIUrl":null,"url":null,"abstract":"In this paper, new molding underfill structure is proposed. It shows many advantages, including a) good package coplanarity b) lower bump stress c) lower 2nd level ball stress d) provide no limitation component design. Mold compound can hold big die and substrate together to keep good package coplanarity and give a uniform interface condition within big die area. Droping in heat spreader design gives the largest flexibility of die size and passive component size/number. Mold compound properties can be tailored to meet solder bump and low-K requirements. In addition, mold compound properties have high potential to meet Pb-free solder bump and low-K requirements. A high reliability, high thermal performance, and low package stress molding flip chip ball grid arrays structure is named terminator FCBGA. It has many benefits, like better coplanarity. high through put (multi pes per shut in molding process), low bump stress, and high thermal performance. In conventional flip chip structure, underfill dispenses and cure processes are a bottleneck due to low through put (dispensing unit by unit). For the high performance demand (high pin counts are necessary), large package/die size with more integrated functions needs to meet reliability criteria. Low k dielectric material, lead free bump especially and the package coplanarity are also challenges for package development. Besides, thermal performance is also a key concern with high power device. Low-k has become a hot topic as most 90nm devices and all 65nm devices utilize low-k dielectric. But low-k materials have very low mechanical strength compared to the traditional dielectric films due to their porous nature, which results in lower cohesive strength. Additionally, the tight bump pitch and low standoff height of future packages reduce the flow performance of conventional liquid capillary underfill (CUF) that results in low productivity (low unit per hour (UPH)) and low throughput. From simulation and reliability data, this new structure can provide strong bump protection and reach high reliability performance and can be applied for low-K chip and all kind of bump composition such as tin-lead, high lead, and lead free.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 8th International Conference on Electronic Packaging Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEPT.2007.4441483","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this paper, new molding underfill structure is proposed. It shows many advantages, including a) good package coplanarity b) lower bump stress c) lower 2nd level ball stress d) provide no limitation component design. Mold compound can hold big die and substrate together to keep good package coplanarity and give a uniform interface condition within big die area. Droping in heat spreader design gives the largest flexibility of die size and passive component size/number. Mold compound properties can be tailored to meet solder bump and low-K requirements. In addition, mold compound properties have high potential to meet Pb-free solder bump and low-K requirements. A high reliability, high thermal performance, and low package stress molding flip chip ball grid arrays structure is named terminator FCBGA. It has many benefits, like better coplanarity. high through put (multi pes per shut in molding process), low bump stress, and high thermal performance. In conventional flip chip structure, underfill dispenses and cure processes are a bottleneck due to low through put (dispensing unit by unit). For the high performance demand (high pin counts are necessary), large package/die size with more integrated functions needs to meet reliability criteria. Low k dielectric material, lead free bump especially and the package coplanarity are also challenges for package development. Besides, thermal performance is also a key concern with high power device. Low-k has become a hot topic as most 90nm devices and all 65nm devices utilize low-k dielectric. But low-k materials have very low mechanical strength compared to the traditional dielectric films due to their porous nature, which results in lower cohesive strength. Additionally, the tight bump pitch and low standoff height of future packages reduce the flow performance of conventional liquid capillary underfill (CUF) that results in low productivity (low unit per hour (UPH)) and low throughput. From simulation and reliability data, this new structure can provide strong bump protection and reach high reliability performance and can be applied for low-K chip and all kind of bump composition such as tin-lead, high lead, and lead free.