2007 8th International Conference on Electronic Packaging Technology最新文献_第10页

A Modelling Approach for Coupling Numerical Analytical Techniques Applied in Microsystems 应用于微系统的耦合数值分析技术建模方法

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441412

Xiangdong Xue, Hua Lu, C. Bailey

{"title":"A Modelling Approach for Coupling Numerical Analytical Techniques Applied in Microsystems","authors":"Xiangdong Xue, Hua Lu, C. Bailey","doi":"10.1109/ICEPT.2007.4441412","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441412","url":null,"abstract":"In this paper, a method for the integration of several numerical analytical techniques that are used in microsystems design and failure analysis is presented. The analytical techniques are categorized into four groups in the discussion, namely the high-fidelity analytical tools, i.e. finite element (FE) method, the fast analytical tools referring to reduced order modeling (ROM); the optimization tools, and probability based analytical tools. The characteristics of these four tools are investigated. The interactions between the four tools are discussed and a methodology for the coupling of these four tools is offered. This methodology consists of three stages, namely reduced order modeling, deterministic optimization and probabilistic optimization. Using this methodology, a case study for optimization of a solder joint is conducted. It is shown that these analysis techniques have mutual relationship of interaction and complementation. Synthetic application of these techniques can fully utilize the advantages of these techniques and satisfy various design requirements. The case study shows that the coupling method of different tools provided by this paper is effective and efficient and it is highly relevant in the design and reliability analysis of microsystems.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126618942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Testing Solder Interconnect Reliability Under Drop Impact Loading Conditions 在跌落冲击载荷条件下测试焊料互连可靠性

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441528

J. Zaal, W. V. van Driel, H. P. Hochstenbach, G.Q. Zhang

{"title":"Testing Solder Interconnect Reliability Under Drop Impact Loading Conditions","authors":"J. Zaal, W. V. van Driel, H. P. Hochstenbach, G.Q. Zhang","doi":"10.1109/ICEPT.2007.4441528","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441528","url":null,"abstract":"A common failure during the lifetime of most mobile devices is failure through dropping. This is nowadays tested by means of the drop impact test, which has been standardized by JEDEC. This method however takes quite some time and has some problems regarding reproducibility. This paper reports the work done on correlating the drop impact test with the cold bump pull that might be a replacement. The way of working is aimed at understanding the mechanical loading that causes failure and not on just fitting data. Therefore the drop impact test has been modeled and an experiment is prepared to verify this model which will be conducted in the near future. The cold bump pull test has been investigated to verify that the test is not biasing the bump into a certain failure mode, results are reported in this paper. The simulations regarding the cold bump pull are also presented as well. The two tests seem to be testing the same phenomena since the results from the CBP are indicating the same things as the drop impact tests but this is not yet proven since both simulation and experimental work is not entirely finished.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115227828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Solutions to the Technological Issues of a Global Packaging Industry 解决全球包装行业的技术问题

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441550

M. Ehlert

引用次数: 0

Fracture Simulation of Solder Joints by a Lattice Model 基于点阵模型的焊点断裂模拟

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441406

Tong An, F. Qin

引用次数: 0

Effect of Cerium Addition on Board Level Reliability of Sn-Ag-Cu Solder Joint 添加铈对Sn-Ag-Cu焊点板级可靠性的影响

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441436

Le Liang, Qian Wang, Zhenqing Zhao

{"title":"Effect of Cerium Addition on Board Level Reliability of Sn-Ag-Cu Solder Joint","authors":"Le Liang, Qian Wang, Zhenqing Zhao","doi":"10.1109/ICEPT.2007.4441436","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441436","url":null,"abstract":"In order to study the effect of rare earth doping on temperature cycle (TC) and drop reliabilities of the SnAgCu solder joints, cerium (Ce) was added to Sn2.5AgO.5Cu solder by the amount of 300, 500, 1000 ppm, respectively. Solder joints were formed. TC and drop tests were conducted. Results show that 500 ppm Ce addition has the least influence on TC reliability of the solder joints, while less or more addition of cerium may deteriorates the TC performance. Most cracks in TC tests occurred in solder bulk or between the solder bulk and the interfacial IMC layer. 300 ppm cerium doped solder joint shows best drop reliability among all samples. Cracks mainly occurred between the interfacial IMC layer and board pad. Drop reliabilities were also tested for samples after high temperature aging (125degC, 300 h). It can be inferred that the more Ce was added, the better thermal stability was achieved in drop tests. Among all high temperature treated samples, 1000 ppm Ce added sample exhibits best drop reliability. Cross-section view of the solder joints show that Ce addition refined the micro structure of the solder joint. Ce tends to segregate on grain boundaries, which restraints the growth of beta-Sn grains and Ag3Sn IMC and in result improves mechanical properties of the solder. Ce also tends to accumulate at the interface between bulk solder and the Cu6Sn5 IMC layer and reacts with Sn, thus depress the interfacial IMC layer growth.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Application of C-mode Scanning Acoustic Microscopy in Packaging c型扫描声显微镜在包装中的应用

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441498

Lili Ma, S. Bao, Dechun Lv, Zhibo Du, Shilan Li

引用次数: 18

Aluminum Ribbon Bonding Technology in a New Package of High Power and Thermal Performance 高功率和热性能的新型封装铝带键合技术

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441448

Huiliang Zhang, Hongbo Yang, Ming Zhou, A. Tsui

引用次数: 4

The Technique Research on FBP FBP技术研究

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441560

Zhizhong Liang, Y. Tao, Y. Qian

{"title":"The Technique Research on FBP","authors":"Zhizhong Liang, Y. Tao, Y. Qian","doi":"10.1109/ICEPT.2007.4441560","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441560","url":null,"abstract":"Summary form only given. As the development of semiconductor manufacturing technology, it will force the packaging technology to develop correspondingly to meet the requests of different IC functions. FBP (Flat Bump Package), designed by JCET, is the package to meet those requests with its high thermal/electrical performance, low interference, strong joint strength and excellent reliability. Furthermore FBP is suitable for many dices such as diode, dynatron, field effect transistors, power IC, RF IC, logic IC, memory IC, driver IC, power management IC and so on. Compared with other leadless packages like QFN/DFN/BCC. FBP has mam improvements like option for epoxy /soft solder/eutectic, no resin bleeding issue, strip testing capability, excellent bond-ability in SMT, die pad mounting to motherboard, low package thickness profile (down to 0.35mm), high I/O capacity (400, 1-3 rows of leads), MCM and embedded passives capability, flexible configuration options and excellent electrical/thermal performance. FBP is JECT patent technology. There are more than 30 patents on FBP domestically and internationally, and more than 10 patents have been authorized by State Intellectual Property Office of P.R.C. In this paper, the special structure and excellent performance of FBP are introduced, described and illustrated graphically.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126621291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Direct Chip Attachment (DCA) Packaging of a 2-D Thermal Flow Sensor 直接芯片连接(DCA)封装的二维热流传感器

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441487

G. Shen, Jian Wu, Hua Zhang, M. Qin, Qing-An Huang

引用次数: 15

Test and Health Monitoring of Microelectronics using RFID 基于RFID的微电子测试与健康监测

2007 8th International Conference on Electronic Packaging Technology Pub Date : 2007-08-01 DOI: 10.1109/ICEPT.2007.4441533

T. Keinhorst, P. Tsigkourakos, M. Yaqoob, W. V. van Driel, G.Q. Zhang

{"title":"Test and Health Monitoring of Microelectronics using RFID","authors":"T. Keinhorst, P. Tsigkourakos, M. Yaqoob, W. V. van Driel, G.Q. Zhang","doi":"10.1109/ICEPT.2007.4441533","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441533","url":null,"abstract":"Interest has been growing in monitoring the ongoing health of systems and products in order to predict failures, provide warning to avoid catastrophic failures, reduce life-cycle costs and enhance their operational efficiency. This paper reviews the current state-of-the-art techniques and innovations of health monitoring of microelectronics using contactless testing. The paper explains the conventional methods of health monitoring (e.g. MTBF method), some 'state-of-research' approaches (e.g. BIT, LCM, UAP, etc) and their advantages and disadvantages as well as some newer methods developed recently (e.g. physics-of-failure based method). The latest technique of health monitoring using Radio Frequency Identification (RFID) is addressed. RFID chips can be used to test the failures in Integrated Circuits (ICs) during the packaging process. This test technique is contactless and cost effective and can be used to test the die after every process in the production line of IC manufacturing. It provides advantages like higher reliability, added functionality and increased throughput. RFID chips that are being used during production cycle for testing can also be used for health monitoring in real time applications ('in-situ' sensors).","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125910549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2