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2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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A 700mV low power pipeline ADC using a novel common mode feedback circuit and offset cancellation technique 采用新型共模反馈电路和失调抵消技术的700mV低功率流水线ADC
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6291994
Guanglei An, C. Hutchens, R. Rennaker
{"title":"A 700mV low power pipeline ADC using a novel common mode feedback circuit and offset cancellation technique","authors":"Guanglei An, C. Hutchens, R. Rennaker","doi":"10.1109/MWSCAS.2012.6291994","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291994","url":null,"abstract":"An 8 bit, 1.5 b/stage fully differential (FD) multiplying digital to analog converter (MDAC) pipeline ADC for use in a smart RFID is presented in this paper. The FD Operational Transconductance Amplifier (OTA) in the MDAC utilizes a novel common mode (CM) amplifier, which is inherently stable demonstrating reduced common mode offset and improved compensation tracking across process. Furthermore, a simple offset cancellation technique robust to device leakage is introduced to correct error due to leakage induced input offset voltage drift. Monte Carlo simulation results show that for the input voltage range of ±400mV, ADC can achieve 8 ENOB with sampling frequency at 16 kHz. Total ADC power consumption is 5.1uA with 0.7V power supply. The ADC was submitted for fabrication in 180nm CMOS with results forth coming.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117070812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reducing test point overhead with don't-cares 用“不关心”来减少测试点开销
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292075
Kai-Hui Chang, Chia-Wei Chang, J. H. Jiang, C. Liu
{"title":"Reducing test point overhead with don't-cares","authors":"Kai-Hui Chang, Chia-Wei Chang, J. H. Jiang, C. Liu","doi":"10.1109/MWSCAS.2012.6292075","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292075","url":null,"abstract":"Test points provide additional control to design logic and can improve circuit testability. Traditionally, test points are activated by a global test enable signal, and routing the signal to the test points can be costly. To address this problem, we propose a new test point structure that utilizes controllability don't-cares to generate local test point activation signals. To support the structure, we propose new methods for extracting don't-cares from assertions and finite state machines in the design. Our empirical evaluation shows that don't-cares exist in many designs and can be used for reducing test point overhead.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129602128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An ultra-low frequency ring oscillator with programmable tracking using a phase-locked loop 一种超低频环形振荡器，采用锁相环进行可编程跟踪
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6291946
Tsung-Hsueh Lee, P. Abshire
{"title":"An ultra-low frequency ring oscillator with programmable tracking using a phase-locked loop","authors":"Tsung-Hsueh Lee, P. Abshire","doi":"10.1109/MWSCAS.2012.6291946","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291946","url":null,"abstract":"This paper presents a programmable ultra-low frequency ring oscillator designed in a 0.5μm CMOS technology with 3.3 V power supply. In normal operation, the oscillator produces a periodic signal without external inputs (other than power and ground). During programming, the oscillator tracks and memorizes the input reference frequency using a phase-locked loop (PLL) architecture. The PLL controls an on-chip nonvolatile memory using a floating gate structure; the voltage on the floating gate node is applied to the voltage-controlled oscillator (VCO) to generate the desired frequency. A high-voltage NMOS is introduced to realize the floating gate control; measurement results show that the breakdown voltage is close to 40 V. Transient simulations indicate that the circuit successfully tracks a desired frequency with maximum period jitter of 0.49 μs at the VCO output which translates to frequency error of 0.88 % at the system output.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128497716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new adustable Schmitt Trigger based on Dual Control Gate-Floating Gate Transistor (DCG-FGT) 基于双控栅-浮栅晶体管(DCG-FGT)的新型可调施密特触发器
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292102
A. Marzaki, V. Bidal, R. Laffont, W. Rahajandraibe, J. Portal, R. Bouchakour
{"title":"A new adustable Schmitt Trigger based on Dual Control Gate-Floating Gate Transistor (DCG-FGT)","authors":"A. Marzaki, V. Bidal, R. Laffont, W. Rahajandraibe, J. Portal, R. Bouchakour","doi":"10.1109/MWSCAS.2012.6292102","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292102","url":null,"abstract":"This paper presents a low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuit is introduced to provide flexibility to program the hysteretic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger has been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and independently adjustable switching voltages VTH- (low switching voltage) and VTH+(high switching voltage).","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129354561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A novel PR channelizer-based architecture for estimation and correction of timing and gain mismatches in two channel TI-ADCs 一种新的基于PR信道的结构，用于估计和校正双通道ti - adc的时序和增益不匹配
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292226
F. Harris, Xiaofei Chen, E. Venosa
{"title":"A novel PR channelizer-based architecture for estimation and correction of timing and gain mismatches in two channel TI-ADCs","authors":"F. Harris, Xiaofei Chen, E. Venosa","doi":"10.1109/MWSCAS.2012.6292226","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292226","url":null,"abstract":"In this paper we present a novel architecture for estimating and correcting time and gain mismatches in a two channel time-interleaved analog-to-digital converter (TI-ADC) which is embedded in a digital communication receiver. TI-ADCs can offer a significant increase in the sample rate however their usage is limited due to the fact that their performance is strongly degraded by timing and gain mismatches between the channels. A standard mismatches estimation approach requires the inclusion of a pilot tone between the signal spectrum and DC. As an effect of the mismatches the aliased copy of the low frequency pilot tone shows up at high frequency where it is processed through an high-pass filter and used for the estimation. After the mismatches cancellation has been performed the low frequency pilot tone needs to be removed from the `clean' signal spectrum which also needs be down converted to base-band. After the down conversion the sample rate has to be adjusted to be commensurate to the new reduced signal bandwidth. Modern software defined radio architectures are based on perfect reconstruction (PR) up and down converter channelizers. In this paper we present a novel architecture for estimating time and gain mismatches in two channel TI-ADCs which is based on PR channelizers and can be naturally embedded in modern digital radio receiver architectures. The PR polyphase channelizer engines provide us a compact and unique solution for filtering the aliased high frequency tone which is used for the mismatch estimation, canceling the low frequency tone and for down converting the corrected signal spectrum to base-band while adjusting its sample rate to the reduced bandwidth.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130331724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A baseband transceiver for multi-mode and multi-band SoC 用于多模式和多频带SoC的基带收发器
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292134
Pan Wu, Chun Zhang, Caifeng Wei, Hanjun Jiang, Zhihua Wang
{"title":"A baseband transceiver for multi-mode and multi-band SoC","authors":"Pan Wu, Chun Zhang, Caifeng Wei, Hanjun Jiang, Zhihua Wang","doi":"10.1109/MWSCAS.2012.6292134","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292134","url":null,"abstract":"In this paper, a baseband transceiver is proposed for IEEE 802.15.4 and for one 2.4G RFID protocol. This transceiver supports OQPSK with direct sequence spread spectrum (DSSS), MSK without spread spectrum, and DBPSK with DSSS. In this design, those three demodulations share most of their hardware blocks to reduce area and power consumption. This baseband transceiver is part of a multi-mode and multi-band SoC for medical monitoring. This design is verified on FPGA and finally fabricated in 0.18um CMOS process with an integrated RF front-end. The area of baseband is 1.7mm2.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130495903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Continuous time ΣΔ modulator, challenges & possibilities 连续时间ΣΔ调制器，挑战与可能性
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292036
A. Das
{"title":"Continuous time ΣΔ modulator, challenges & possibilities","authors":"A. Das","doi":"10.1109/MWSCAS.2012.6292036","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292036","url":null,"abstract":"Single-bit SDM is not very suitable for wide bandwidth and high dynamic range applications even though they are the perfect choice in deep submicron digital process. This paper describes few novel approaches which achieves close to multi-bit modulator performance without losing the advantage of the single-bit modulator.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114309915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Error correction circuits for bio-implantable electronics 生物植入式电子器件纠错电路
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6291981
C. Winstead, Yi Luo
{"title":"Error correction circuits for bio-implantable electronics","authors":"C. Winstead, Yi Luo","doi":"10.1109/MWSCAS.2012.6291981","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291981","url":null,"abstract":"Methods are reviewed for achieving high data rates in bio-implantable devices. Particular attention is given to cortical stimulator arrays for restoring vision. Error-correction codes (ECC) are shown to be essential to obtain reliable operation in next-generation high-rate implants. A survey of reported ECC implementations is presented, and power-vs-performance tradeoffs are revealed after re-scaling to remove differences in technology and clock speed. Recommendations are offered for realizing high-rate ECC circuits within the tight power constraints of implantable device applications.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116488381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current 控制电感电流的绝热充放电过程中的能量耗散降低
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292208
S. Nakata, Ryota Honda, H. Makino, Hiroki Morimura, Y. Matsuda
{"title":"Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current","authors":"S. Nakata, Ryota Honda, H. Makino, Hiroki Morimura, Y. Matsuda","doi":"10.1109/MWSCAS.2012.6292208","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292208","url":null,"abstract":"Adiabatic charging and discharging of a capacitor with an inductor current by controlling switching transistors is demonstrated experimentally. First, we designed an eight-step charging and discharging circuit. The switching transistor ratio is designed to range from zero to one in one-eighth steps. By changing the switching transistor ratio stepwise, output voltage is generated stepwise. Using the stepwise voltage, adiabatic charging and discharging can be performed. In N-step charging, it is clarified that the energy dissipation is reduced to 1/N from the measurement of the power supply current, compared with the conventional charging and discharging of a capacitor.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114766557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Low power data acquisition for microImplant biometric monitoring 微植入生物识别监测的低功耗数据采集
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292135
T. Khanna
{"title":"Low power data acquisition for microImplant biometric monitoring","authors":"T. Khanna","doi":"10.1109/MWSCAS.2012.6292135","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292135","url":null,"abstract":"In this paper, a scheme for data acquisition suited to long term biometric monitoring is presented for microImplants, in particular as applied to Parkinson's tremor monitoring. The system application informs the circuit design and combines the techniques of compressive sensing and adiabatic charging, we can show an effective improvement in the FOM of a 7-bit SAR ADC fabricated in a 0.18um process.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124319054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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